From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 101523858D35 for ; Thu, 16 Dec 2021 05:59:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 101523858D35 X-IronPort-AV: E=McAfee;i="6200,9189,10199"; a="219425375" X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="219425375" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2021 21:59:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="755715500" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga005.fm.intel.com with ESMTP; 15 Dec 2021 21:59:41 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1BG5xd3P016206; Wed, 15 Dec 2021 21:59:40 -0800 From: liuhongt To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Optimize bit_and op1 float_vector_all_ones_operands to op1. Date: Thu, 16 Dec 2021 13:59:39 +0800 Message-Id: <20211216055939.13323-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Dec 2021 05:59:43 -0000 Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/98468 * config/i386/sse.md (*bit_and_float_vector_all_ones): New pre-reload splitter. gcc/testsuite/ChangeLog: * gcc.target/i386/pr98468.c: New test. --- gcc/config/i386/sse.md | 12 +++++++++ gcc/testsuite/gcc.target/i386/pr98468.c | 35 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr98468.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5421fb51684..a715263740b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4432,6 +4432,18 @@ (define_insn "*3" (const_string "") (const_string "XI")))]) +;; Generic part doesn't support the simpliciation of logic operation with +;; float_vector_all_ones_operand since it's not valid rtl. Add combine spiltter +;; for them, it should be safe since there's no SIMD Floating-Point Exceptions. +(define_insn_and_split "*bit_and_float_vector_all_ones" + [(set (match_operand:VFB 0 "nonimmediate_operand") + (and:VFB (match_operand:VFB 1 "nonimmediate_operand") + (match_operand:VFB 2 "float_vector_all_ones_operand")))] + "TARGET_SSE && ix86_pre_reload_split ()" + "#" + "&& 1" + [(set (match_dup 0) (match_dup 1))]) + (define_expand "copysign3" [(set (match_dup 4) (and:VFB diff --git a/gcc/testsuite/gcc.target/i386/pr98468.c b/gcc/testsuite/gcc.target/i386/pr98468.c new file mode 100644 index 00000000000..ca3aa256c52 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98468.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512dq -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-not "vxorp" } } */ +/* { dg-final { scan-assembler-not "vandnp" } } */ + +#include +__m128 f(__m128 val) +{ + return _mm_andnot_ps(_mm_set_ps1(0.0f), val); +} + +__m256 f2(__m256 val) +{ + return _mm256_andnot_ps(_mm256_set1_ps(0.0f), val); +} + +__m512 f3(__m512 val) +{ + return _mm512_andnot_ps(_mm512_set1_ps(0.0f), val); +} + +__m128d f4(__m128d val) +{ + return _mm_andnot_pd(_mm_set_pd1(0.0), val); +} + +__m256d f5(__m256d val) +{ + return _mm256_andnot_pd(_mm256_set1_pd(0.0), val); +} + +__m512d f6(__m512d val) +{ + return _mm512_andnot_pd(_mm512_set1_pd(0.0), val); +} -- 2.18.1