From: Segher Boessenkool <segher@kernel.crashing.org>
To: David Edelsohn <dje.gcc@gmail.com>
Cc: HAO CHEN GUI <guihaoc@linux.ibm.com>,
gcc-patches <gcc-patches@gcc.gnu.org>,
Bill Schmidt <wschmidt@linux.ibm.com>
Subject: Re: [PATCH, rs6000] Implement mffscrni pattern
Date: Sat, 18 Dec 2021 15:25:49 -0600 [thread overview]
Message-ID: <20211218212549.GT614@gate.crashing.org> (raw)
In-Reply-To: <CAGWvnyk8-Ed3--M8CkYsgOWESBjhAz9fWdFncwvQ=SymNjvRvg@mail.gmail.com>
On Fri, Dec 17, 2021 at 10:33:12PM -0500, David Edelsohn wrote:
> On Thu, Dec 16, 2021 at 9:43 PM HAO CHEN GUI <guihaoc@linux.ibm.com> wrote:
> > +(define_insn "rs6000_mffscrni"
> > + [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
> > + (unspec_volatile:DF [(match_operand:DF 1 "u2bit_cint_operand" "n")]
>
> Why is this input operand 1 DFmode? This is a 2 bit integer value.
> This pattern is called from rs6000_set_fpscr_rn with an SImode
> operand, and it seems that this should be SImode as well.
Yup. This predicate will only allow const_int, and matching a const_int
ignores the mode, so most (or all?) things will work whatever mode you
give here. But only MODE_INT modes make sense (and possibly VOIDmode,
but VOIDmode in machine descriptions means anything is allowed, also not
what you want here).
Segher
next prev parent reply other threads:[~2021-12-18 21:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-17 2:43 HAO CHEN GUI
2021-12-18 3:33 ` David Edelsohn
2021-12-18 21:25 ` Segher Boessenkool [this message]
2021-12-20 5:55 HAO CHEN GUI
2021-12-20 15:55 ` David Edelsohn
2021-12-20 23:14 ` Segher Boessenkool
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