From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 64C4F3858D35 for ; Tue, 4 Jan 2022 03:27:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 64C4F3858D35 X-IronPort-AV: E=McAfee;i="6200,9189,10216"; a="229463971" X-IronPort-AV: E=Sophos;i="5.88,258,1635231600"; d="scan'208";a="229463971" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2022 19:27:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,258,1635231600"; d="scan'208";a="620494693" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 03 Jan 2022 19:27:37 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 2043RZ21001158; Mon, 3 Jan 2022 19:27:36 -0800 From: liuhongt To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Force_reg operand 1. Date: Tue, 4 Jan 2022 11:27:35 +0800 Message-Id: <20220104032735.54350-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jan 2022 03:27:41 -0000 Avoid ICE of move pattern from memory to memory. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Pushed to trunk. gcc/ChangeLog: PR target/103895 * config/i386/sse.md (*bit_and_float_vector_all_ones): Force_reg operand 1 to avoid ICE. gcc/testsuite/ChangeLog: * gcc.target/i386/pr103895.c: New test. --- gcc/config/i386/sse.md | 3 ++- gcc/testsuite/gcc.target/i386/pr103895.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr103895.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 033b60d9aa2..fa1d56ae3e3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4750,7 +4750,8 @@ (define_insn_and_split "*bit_and_float_vector_all_ones" "TARGET_SSE && ix86_pre_reload_split ()" "#" "&& 1" - [(set (match_dup 0) (match_dup 1))]) + [(set (match_dup 0) (match_dup 1))] + "operands[1] = force_reg (mode, operands[1]);") (define_expand "copysign3" [(set (match_dup 4) diff --git a/gcc/testsuite/gcc.target/i386/pr103895.c b/gcc/testsuite/gcc.target/i386/pr103895.c new file mode 100644 index 00000000000..40b827806e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103895.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -ffloat-store" } */ + +#include +typedef float vFloat __attribute__((__vector_size__(16))); +float bar_dr; +vFloat bar_f1; +void bar() { + static vFloat m0; + vFloat fa1 = _mm_andnot_ps(m0, bar_f1); + __attribute__((__vector_size__(2 * sizeof(double)))) double v3 = + _mm_cvtps_pd(fa1); + vFloat r1 = _mm_cvtpd_ps(v3); + _mm_storeu_ps(&bar_dr, r1); +} + -- 2.18.1