From: Christophe Lyon <christophe.lyon@foss.st.com>
To: <gcc-patches@gcc.gnu.org>
Subject: [PATCH v3 10/15] arm: Convert remaining MVE vcmp builtins to predicate qualifiers
Date: Thu, 13 Jan 2022 15:56:20 +0100 [thread overview]
Message-ID: <20220113145645.4077141-11-christophe.lyon@foss.st.com> (raw)
In-Reply-To: <20220113145645.4077141-1-christophe.lyon@foss.st.com>
This is mostly a mechanical change, only tested by the intrinsics
expansion tests.
2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (BINOP_UNONE_NONE_NONE_QUALIFIERS):
Delete.
(TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ...
(TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this.
(TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New.
* config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new
predicated qualifiers.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>)
(mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 36d71ab1a13..9cc192ddb9a 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -438,12 +438,6 @@ arm_binop_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define BINOP_NONE_NONE_UNONE_QUALIFIERS \
(arm_binop_none_none_unone_qualifiers)
-static enum arm_type_qualifiers
-arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_unsigned, qualifier_none, qualifier_none };
-#define BINOP_UNONE_NONE_NONE_QUALIFIERS \
- (arm_binop_unone_none_none_qualifiers)
-
static enum arm_type_qualifiers
arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_predicate, qualifier_none, qualifier_none };
@@ -504,10 +498,10 @@ arm_ternop_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
(arm_ternop_unone_unone_imm_unone_qualifiers)
static enum arm_type_qualifiers
-arm_ternop_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_unsigned, qualifier_none, qualifier_none, qualifier_unsigned };
-#define TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS \
- (arm_ternop_unone_none_none_unone_qualifiers)
+arm_ternop_pred_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_predicate, qualifier_none, qualifier_none, qualifier_predicate };
+#define TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS \
+ (arm_ternop_pred_none_none_pred_qualifiers)
static enum arm_type_qualifiers
arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
@@ -553,6 +547,13 @@ arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \
(arm_ternop_unone_unone_unone_pred_qualifiers)
+static enum arm_type_qualifiers
+arm_ternop_pred_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_predicate, qualifier_unsigned, qualifier_unsigned,
+ qualifier_predicate };
+#define TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS \
+ (arm_ternop_pred_unone_unone_pred_qualifiers)
+
static enum arm_type_qualifiers
arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none };
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index 44b41eab4c5..b7ebbcab87f 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -118,9 +118,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_UNONE, vaddvq_p_u, v16qi, v8hi, v4si)
@@ -142,17 +142,17 @@ VAR3 (BINOP_UNONE_UNONE_NONE, vbrsrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si)
-VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si)
+VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vsubq_s, v16qi, v8hi, v4si)
@@ -218,17 +218,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshlltq_n_u, v16qi, v8hi)
VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi)
VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si)
VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf)
-VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf)
+VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf)
VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf)
VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si)
@@ -285,7 +285,7 @@ VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaq_s, v4si)
VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_u, v4si)
VAR2 (TERNOP_NONE_NONE_UNONE_UNONE, vcvtq_m_to_f_u, v8hf, v4sf)
VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtq_m_to_f_s, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_f, v8hf, v4sf)
VAR3 (TERNOP_UNONE_NONE_UNONE_IMM, vshlcq_carry_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_carry_u, v16qi, v8hi, v4si)
VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshrunbq_n_s, v8hi, v4si)
@@ -306,14 +306,14 @@ VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmladavaq_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vminvq_p_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmaxvq_p_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vdupq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpneq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmphiq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpeqq_m_n_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_u, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vcmpcsq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpneq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmphiq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpeqq_m_n_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_u, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_UNONE_UNONE_PRED, vcmpcsq_m_n_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vclzq_m_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddvaq_p_u, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vsriq_n_u, v16qi, v8hi, v4si)
@@ -326,18 +326,18 @@ VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminavq_p_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vminaq_m_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxavq_p_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_UNONE_UNONE_NONE_UNONE, vmaxaq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_s, v16qi, v8hi, v4si)
-VAR3 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_s, v16qi, v8hi, v4si)
+VAR3 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vshlq_m_r_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrshlq_m_n_s, v16qi, v8hi, v4si)
VAR3 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_s, v16qi, v8hi, v4si)
@@ -405,17 +405,17 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqshrunbq_n_s, v8hi, v4si)
VAR2 (TERNOP_UNONE_UNONE_NONE_IMM, vqrshruntq_n_s, v8hi, v4si)
VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vorrq_m_n_u, v8hi, v4si)
VAR2 (TERNOP_UNONE_UNONE_IMM_UNONE, vmvnq_m_n_u, v8hi, v4si)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_n_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpneq_m_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_n_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpltq_m_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_n_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpleq_m_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_n_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgtq_m_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_n_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpgeq_m_f, v8hf, v4sf)
-VAR2 (TERNOP_UNONE_NONE_NONE_UNONE, vcmpeqq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpneq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpltq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpleq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgtq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_n_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpgeq_m_f, v8hf, v4sf)
+VAR2 (TERNOP_PRED_NONE_NONE_PRED, vcmpeqq_m_n_f, v8hf, v4sf)
VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndxq_m_f, v8hf, v4sf)
VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndq_m_f, v8hf, v4sf)
VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrndpq_m_f, v8hf, v4sf)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 35564e870bc..c5cdc06c548 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
;;
(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE"
@@ -1943,8 +1943,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_f<mode>"
;;
(define_insn "@mve_vcmp<mve_cmp_op>q_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (MVE_FP_COMPARISONS:<MVE_VPRED> (match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -2593,10 +2593,10 @@ (define_insn "mve_vbicq_m_n_<supf><mode>"
;;
(define_insn "mve_vcmpeqq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPEQQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -2809,10 +2809,10 @@ (define_insn "mve_vclzq_m_<supf><mode>"
;;
(define_insn "mve_vcmpcsq_m_n_u<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPCSQ_M_N_U))
]
"TARGET_HAVE_MVE"
@@ -2825,10 +2825,10 @@ (define_insn "mve_vcmpcsq_m_n_u<mode>"
;;
(define_insn "mve_vcmpcsq_m_u<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPCSQ_M_U))
]
"TARGET_HAVE_MVE"
@@ -2841,10 +2841,10 @@ (define_insn "mve_vcmpcsq_m_u<mode>"
;;
(define_insn "mve_vcmpeqq_m_n_<supf><mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPEQQ_M_N))
]
"TARGET_HAVE_MVE"
@@ -2857,10 +2857,10 @@ (define_insn "mve_vcmpeqq_m_n_<supf><mode>"
;;
(define_insn "mve_vcmpeqq_m_<supf><mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPEQQ_M))
]
"TARGET_HAVE_MVE"
@@ -2873,10 +2873,10 @@ (define_insn "mve_vcmpeqq_m_<supf><mode>"
;;
(define_insn "mve_vcmpgeq_m_n_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGEQ_M_N_S))
]
"TARGET_HAVE_MVE"
@@ -2889,10 +2889,10 @@ (define_insn "mve_vcmpgeq_m_n_s<mode>"
;;
(define_insn "mve_vcmpgeq_m_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGEQ_M_S))
]
"TARGET_HAVE_MVE"
@@ -2905,10 +2905,10 @@ (define_insn "mve_vcmpgeq_m_s<mode>"
;;
(define_insn "mve_vcmpgtq_m_n_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGTQ_M_N_S))
]
"TARGET_HAVE_MVE"
@@ -2921,10 +2921,10 @@ (define_insn "mve_vcmpgtq_m_n_s<mode>"
;;
(define_insn "mve_vcmpgtq_m_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGTQ_M_S))
]
"TARGET_HAVE_MVE"
@@ -2937,10 +2937,10 @@ (define_insn "mve_vcmpgtq_m_s<mode>"
;;
(define_insn "mve_vcmphiq_m_n_u<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPHIQ_M_N_U))
]
"TARGET_HAVE_MVE"
@@ -2953,10 +2953,10 @@ (define_insn "mve_vcmphiq_m_n_u<mode>"
;;
(define_insn "mve_vcmphiq_m_u<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPHIQ_M_U))
]
"TARGET_HAVE_MVE"
@@ -2969,10 +2969,10 @@ (define_insn "mve_vcmphiq_m_u<mode>"
;;
(define_insn "mve_vcmpleq_m_n_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLEQ_M_N_S))
]
"TARGET_HAVE_MVE"
@@ -2985,10 +2985,10 @@ (define_insn "mve_vcmpleq_m_n_s<mode>"
;;
(define_insn "mve_vcmpleq_m_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLEQ_M_S))
]
"TARGET_HAVE_MVE"
@@ -3001,10 +3001,10 @@ (define_insn "mve_vcmpleq_m_s<mode>"
;;
(define_insn "mve_vcmpltq_m_n_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLTQ_M_N_S))
]
"TARGET_HAVE_MVE"
@@ -3017,10 +3017,10 @@ (define_insn "mve_vcmpltq_m_n_s<mode>"
;;
(define_insn "mve_vcmpltq_m_s<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLTQ_M_S))
]
"TARGET_HAVE_MVE"
@@ -3033,10 +3033,10 @@ (define_insn "mve_vcmpltq_m_s<mode>"
;;
(define_insn "mve_vcmpneq_m_n_<supf><mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPNEQ_M_N))
]
"TARGET_HAVE_MVE"
@@ -3049,10 +3049,10 @@ (define_insn "mve_vcmpneq_m_n_<supf><mode>"
;;
(define_insn "mve_vcmpneq_m_<supf><mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPNEQ_M))
]
"TARGET_HAVE_MVE"
@@ -3770,10 +3770,10 @@ (define_insn "mve_vcmlaq<mve_rot><mode>"
;;
(define_insn "mve_vcmpeqq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPEQQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3786,10 +3786,10 @@ (define_insn "mve_vcmpeqq_m_n_f<mode>"
;;
(define_insn "mve_vcmpgeq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGEQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3802,10 +3802,10 @@ (define_insn "mve_vcmpgeq_m_f<mode>"
;;
(define_insn "mve_vcmpgeq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGEQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3818,10 +3818,10 @@ (define_insn "mve_vcmpgeq_m_n_f<mode>"
;;
(define_insn "mve_vcmpgtq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGTQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3834,10 +3834,10 @@ (define_insn "mve_vcmpgtq_m_f<mode>"
;;
(define_insn "mve_vcmpgtq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPGTQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3850,10 +3850,10 @@ (define_insn "mve_vcmpgtq_m_n_f<mode>"
;;
(define_insn "mve_vcmpleq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLEQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3866,10 +3866,10 @@ (define_insn "mve_vcmpleq_m_f<mode>"
;;
(define_insn "mve_vcmpleq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLEQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3882,10 +3882,10 @@ (define_insn "mve_vcmpleq_m_n_f<mode>"
;;
(define_insn "mve_vcmpltq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLTQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3898,10 +3898,10 @@ (define_insn "mve_vcmpltq_m_f<mode>"
;;
(define_insn "mve_vcmpltq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPLTQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3914,10 +3914,10 @@ (define_insn "mve_vcmpltq_m_n_f<mode>"
;;
(define_insn "mve_vcmpneq_m_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPNEQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3930,10 +3930,10 @@ (define_insn "mve_vcmpneq_m_f<mode>"
;;
(define_insn "mve_vcmpneq_m_n_f<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (unspec:<MVE_VPRED> [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCMPNEQ_M_N_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
--
2.25.1
next prev parent reply other threads:[~2022-01-13 15:00 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-13 14:56 [PATCH v3 00/15] ARM/MVE use vectors of boolean for predicates Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 01/15] arm: Add new tests for comparison vectorization with Neon and MVE Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 02/15] arm: Add tests for PR target/100757 Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 03/15] arm: Add tests for PR target/101325 Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 04/15] arm: Add GENERAL_AND_VPR_REGS regclass Christophe Lyon
2022-01-19 18:17 ` Andre Vieira (lists)
2022-01-20 9:14 ` Christophe Lyon
2022-01-20 9:43 ` Andre Vieira (lists)
2022-01-20 10:40 ` Richard Sandiford
2022-01-20 10:45 ` Andre Vieira (lists)
2022-01-27 16:21 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 05/15] arm: Add support for VPR_REG in arm_class_likely_spilled_p Christophe Lyon
2022-01-19 18:25 ` Andre Vieira (lists)
2022-01-20 9:20 ` Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 06/15] arm: Fix mve_vmvnq_n_<supf><mode> argument mode Christophe Lyon
2022-01-19 19:03 ` Andre Vieira (lists)
2022-01-20 9:23 ` Christophe Lyon
2022-01-20 9:38 ` Andre Simoes Dias Vieira
2022-01-20 9:44 ` Christophe Lyon
2022-01-20 10:45 ` Richard Sandiford
2022-01-20 11:06 ` Andre Vieira (lists)
2022-01-13 14:56 ` [PATCH v3 07/15] arm: Implement MVE predicates as vectors of booleans Christophe Lyon
2022-01-21 11:20 ` Andre Vieira (lists)
2022-01-21 22:30 ` Christophe Lyon
2022-01-27 16:28 ` Kyrylo Tkachov
2022-01-27 18:10 ` Christophe Lyon
2022-01-31 18:01 ` Richard Sandiford
2022-01-31 22:57 ` Christophe Lyon
2022-02-01 3:42 ` Richard Sandiford
2022-02-02 16:51 ` Christophe Lyon
2022-02-04 9:42 ` Richard Sandiford
2022-02-04 9:54 ` Richard Sandiford
2022-02-17 15:39 ` Christophe Lyon
2022-02-21 18:18 ` Richard Sandiford
2022-01-13 14:56 ` [PATCH v3 08/15] arm: Implement auto-vectorized MVE comparisons with vectors of boolean predicates Christophe Lyon
2022-01-27 16:37 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 09/15] arm: Fix vcond_mask expander for MVE (PR target/100757) Christophe Lyon
2022-01-27 16:55 ` Kyrylo Tkachov
2022-01-13 14:56 ` Christophe Lyon [this message]
2022-01-13 14:56 ` [PATCH v3 11/15] arm: Convert more MVE builtins to predicate qualifiers Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 12/15] arm: Convert more load/store " Christophe Lyon
2022-01-27 16:56 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 13/15] arm: Convert more MVE/CDE " Christophe Lyon
2022-01-27 16:56 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 14/15] arm: Add VPR_REG to ALL_REGS Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 15/15] arm: Fix constraint check for V8HI in mve_vector_mem_operand Christophe Lyon
2022-01-14 17:03 ` [arm] MVE: Relax addressing modes for full loads and stores Andre Vieira (lists)
2022-01-17 7:48 ` Christophe Lyon
2022-03-07 14:16 ` Andre Vieira (lists)
2022-03-07 16:14 ` Kyrylo Tkachov
2022-01-14 13:18 ` [PATCH v3 00/15] ARM/MVE use vectors of boolean for predicates Christophe Lyon
2022-01-14 13:33 ` Richard Biener
2022-01-14 14:22 ` Kyrylo Tkachov
2022-01-26 8:40 ` Christophe Lyon
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