From: Christophe Lyon <christophe.lyon@foss.st.com>
To: <gcc-patches@gcc.gnu.org>
Subject: [PATCH v3 13/15] arm: Convert more MVE/CDE builtins to predicate qualifiers
Date: Thu, 13 Jan 2022 15:56:23 +0100 [thread overview]
Message-ID: <20220113145645.4077141-14-christophe.lyon@foss.st.com> (raw)
In-Reply-To: <20220113145645.4077141-1-christophe.lyon@foss.st.com>
This patch covers a few non-load/store builtins where we do not use
the <mode> iterator and thus we cannot use <MVE_vpred>.
2022-01-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/
PR target/100757
PR target/101325
* config/arm/arm-builtins.c (CX_UNARY_UNONE_QUALIFIERS): Use
predicate.
(CX_BINARY_UNONE_QUALIFIERS): Likewise.
(CX_TERNARY_UNONE_QUALIFIERS): Likewise.
(TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
(QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
(QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete.
* config/arm/arm_mve_builtins.def: Use predicated qualifiers.
* config/arm/mve.md: Use VxBI instead of HI.
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 73678a00398..f9437752a22 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -295,7 +295,7 @@ static enum arm_type_qualifiers
arm_cx_unary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_immediate, qualifier_none,
qualifier_unsigned_immediate,
- qualifier_unsigned };
+ qualifier_predicate };
#define CX_UNARY_UNONE_QUALIFIERS (arm_cx_unary_unone_qualifiers)
/* T (immediate, T, T, unsigned immediate). */
@@ -304,7 +304,7 @@ arm_cx_binary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_immediate,
qualifier_none, qualifier_none,
qualifier_unsigned_immediate,
- qualifier_unsigned };
+ qualifier_predicate };
#define CX_BINARY_UNONE_QUALIFIERS (arm_cx_binary_unone_qualifiers)
/* T (immediate, T, T, T, unsigned immediate). */
@@ -313,7 +313,7 @@ arm_cx_ternary_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_immediate,
qualifier_none, qualifier_none, qualifier_none,
qualifier_unsigned_immediate,
- qualifier_unsigned };
+ qualifier_predicate };
#define CX_TERNARY_UNONE_QUALIFIERS (arm_cx_ternary_unone_qualifiers)
/* The first argument (return type) of a store should be void type,
@@ -509,12 +509,6 @@ arm_ternop_none_none_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS \
(arm_ternop_none_none_none_imm_qualifiers)
-static enum arm_type_qualifiers
-arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_none, qualifier_none, qualifier_none, qualifier_unsigned };
-#define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \
- (arm_ternop_none_none_none_unone_qualifiers)
-
static enum arm_type_qualifiers
arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_predicate };
@@ -567,13 +561,6 @@ arm_quadop_unone_unone_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS \
(arm_quadop_unone_unone_none_none_pred_qualifiers)
-static enum arm_type_qualifiers
-arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_none, qualifier_none, qualifier_none, qualifier_none,
- qualifier_unsigned };
-#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \
- (arm_quadop_none_none_none_none_unone_qualifiers)
-
static enum arm_type_qualifiers
arm_quadop_none_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_none, qualifier_none,
@@ -588,13 +575,6 @@ arm_quadop_none_none_none_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS \
(arm_quadop_none_none_none_imm_pred_qualifiers)
-static enum arm_type_qualifiers
-arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS]
- = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
- qualifier_unsigned, qualifier_unsigned };
-#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \
- (arm_quadop_unone_unone_unone_unone_unone_qualifiers)
-
static enum arm_type_qualifiers
arm_quadop_unone_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned,
diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def
index 7db6d47867e..1c8ee34f5cb 100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -87,8 +87,8 @@ VAR4 (BINOP_UNONE_UNONE_UNONE, vcreateq_u, v16qi, v8hi, v4si, v2di)
VAR4 (BINOP_NONE_UNONE_UNONE, vcreateq_s, v16qi, v8hi, v4si, v2di)
VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si)
-VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si)
-VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si)
+VAR1 (BINOP_NONE_NONE_PRED, vaddlvq_p_s, v4si)
+VAR1 (BINOP_UNONE_UNONE_PRED, vaddlvq_p_u, v4si)
VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si)
VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si)
VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si)
@@ -465,20 +465,20 @@ VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqshrnbq_n_s, v8hi, v4si)
VAR2 (TERNOP_NONE_NONE_NONE_IMM, vqrshrntq_n_s, v8hi, v4si)
VAR2 (TERNOP_NONE_NONE_IMM_PRED, vorrq_m_n_s, v8hi, v4si)
VAR2 (TERNOP_NONE_NONE_IMM_PRED, vmvnq_m_n_s, v8hi, v4si)
-VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrmlaldavhq_p_u, v4si)
-VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev16q_m_u, v16qi)
-VAR1 (TERNOP_UNONE_UNONE_UNONE_UNONE, vaddlvaq_p_u, v4si)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhxq_p_s, v4si)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlsldavhq_p_s, v4si)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhxq_p_s, v4si)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrmlaldavhq_p_s, v4si)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_f, v8hf)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vrev16q_m_s, v16qi)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f32_f16, v4sf)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvttq_m_f16_f32, v8hf)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f32_f16, v4sf)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vcvtbq_m_f16_f32, v8hf)
-VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrmlaldavhq_p_u, v4si)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vrev16q_m_u, v16qi)
+VAR1 (TERNOP_UNONE_UNONE_UNONE_PRED, vaddlvaq_p_u, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhxq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlsldavhq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhxq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrmlaldavhq_p_s, v4si)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev32q_m_f, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vrev16q_m_s, v16qi)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f32_f16, v4sf)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvttq_m_f16_f32, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f32_f16, v4sf)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vcvtbq_m_f16_f32, v8hf)
+VAR1 (TERNOP_NONE_NONE_NONE_PRED, vaddlvaq_p_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si)
VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si)
@@ -629,11 +629,11 @@ VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrntq_m_n_s, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqshrnbq_m_n_s, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrntq_m_n_s, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vqrshrnbq_m_n_s, v8hi, v4si)
-VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vrmlaldavhaq_p_u, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaxq_p_s, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlsldavhaq_p_s, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaxq_p_s, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vrmlaldavhaq_p_s, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vrmlaldavhaq_p_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaxq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlsldavhaq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaxq_p_s, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vrmlaldavhaq_p_s, v4si)
VAR2 (QUADOP_UNONE_UNONE_NONE_IMM_PRED, vcvtq_m_n_from_f_u, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_NONE_IMM_PRED, vcvtq_m_n_from_f_s, v8hi, v4si)
VAR2 (QUADOP_NONE_NONE_NONE_NONE_PRED, vbrsrq_m_n_f, v8hf, v4sf)
@@ -845,14 +845,14 @@ VAR1 (BINOP_NONE_NONE_NONE, vsbciq_s, v4si)
VAR1 (BINOP_UNONE_UNONE_UNONE, vsbciq_u, v4si)
VAR1 (BINOP_NONE_NONE_NONE, vsbcq_s, v4si)
VAR1 (BINOP_UNONE_UNONE_UNONE, vsbcq_u, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadciq_m_s, v4si)
-VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadciq_m_u, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vadcq_m_s, v4si)
-VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vadcq_m_u, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbciq_m_s, v4si)
-VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbciq_m_u, v4si)
-VAR1 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsbcq_m_s, v4si)
-VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadciq_m_s, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadciq_m_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vadcq_m_s, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vadcq_m_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbciq_m_s, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbciq_m_u, v4si)
+VAR1 (QUADOP_NONE_NONE_NONE_NONE_PRED, vsbcq_m_s, v4si)
+VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED, vsbcq_m_u, v4si)
VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9633b7187f6..41e85b1a278 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -826,7 +826,7 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:HI 2 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 2 "vpr_register_operand" "Up")]
VADDLVQ_P))
]
"TARGET_HAVE_MVE"
@@ -3739,7 +3739,7 @@ (define_insn "mve_vaddlvaq_p_<supf>v4si"
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 3 "vpr_register_operand" "Up")]
VADDLVAQ_P))
]
"TARGET_HAVE_MVE"
@@ -3949,7 +3949,7 @@ (define_insn "mve_vcvtbq_m_f16_f32v8hf"
(set (match_operand:V8HF 0 "s_register_operand" "=w")
(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
(match_operand:V4SF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCVTBQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3965,7 +3965,7 @@ (define_insn "mve_vcvtbq_m_f32_f16v4sf"
(set (match_operand:V4SF 0 "s_register_operand" "=w")
(unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
(match_operand:V8HF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCVTBQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3981,7 +3981,7 @@ (define_insn "mve_vcvttq_m_f16_f32v8hf"
(set (match_operand:V8HF 0 "s_register_operand" "=w")
(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
(match_operand:V4SF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCVTTQ_M_F16_F32))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -3997,7 +3997,7 @@ (define_insn "mve_vcvttq_m_f32_f16v4sf"
(set (match_operand:V4SF 0 "s_register_operand" "=w")
(unspec:V4SF [(match_operand:V4SF 1 "s_register_operand" "0")
(match_operand:V8HF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VCVTTQ_M_F32_F16))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -4595,7 +4595,7 @@ (define_insn "mve_vrev32q_m_fv8hf"
(set (match_operand:V8HF 0 "s_register_operand" "=w")
(unspec:V8HF [(match_operand:V8HF 1 "s_register_operand" "0")
(match_operand:V8HF 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VREV32Q_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -4659,7 +4659,7 @@ (define_insn "mve_vrmlaldavhxq_p_sv4si"
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VRMLALDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -4691,7 +4691,7 @@ (define_insn "mve_vrmlsldavhq_p_sv4si"
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VRMLSLDAVHQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -4707,7 +4707,7 @@ (define_insn "mve_vrmlsldavhxq_p_sv4si"
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
VRMLSLDAVHXQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -4932,7 +4932,7 @@ (define_insn "mve_vrev16q_m_<supf>v16qi"
(set (match_operand:V16QI 0 "s_register_operand" "=w")
(unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "0")
(match_operand:V16QI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:V16BI 3 "vpr_register_operand" "Up")]
VREV16Q_M))
]
"TARGET_HAVE_MVE"
@@ -4964,7 +4964,7 @@ (define_insn "mve_vrmlaldavhq_p_<supf>v4si"
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 3 "vpr_register_operand" "Up")]
VRMLALDAVHQ_P))
]
"TARGET_HAVE_MVE"
@@ -6233,7 +6233,7 @@ (define_insn "mve_vrmlaldavhaq_p_sv4si"
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
VRMLALDAVHAQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -6556,7 +6556,7 @@ (define_insn "mve_vrmlaldavhaq_p_uv4si"
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
VRMLALDAVHAQ_P_U))
]
"TARGET_HAVE_MVE"
@@ -6573,7 +6573,7 @@ (define_insn "mve_vrmlaldavhaxq_p_sv4si"
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
VRMLALDAVHAXQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -6590,7 +6590,7 @@ (define_insn "mve_vrmlsldavhaq_p_sv4si"
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
VRMLSLDAVHAQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -6607,7 +6607,7 @@ (define_insn "mve_vrmlsldavhaxq_p_sv4si"
(unspec:DI [(match_operand:DI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
VRMLSLDAVHAXQ_P_S))
]
"TARGET_HAVE_MVE"
@@ -7528,7 +7528,7 @@ (define_insn "mve_vldrhq_<supf><mode>"
(define_insn "mve_vldrhq_z_fv8hf"
[(set (match_operand:V8HF 0 "s_register_operand" "=w")
(unspec:V8HF [(match_operand:V8HI 1 "mve_memory_operand" "Ux")
- (match_operand:HI 2 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
VLDRHQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -8303,7 +8303,7 @@ (define_insn "mve_vstrwq_fv4sf"
(define_insn "mve_vstrwq_p_fv4sf"
[(set (match_operand:V4SI 0 "mve_memory_operand" "=Ux")
(unspec:V4SI [(match_operand:V4SF 1 "s_register_operand" "w")
- (match_operand:HI 2 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
VSTRWQ_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -9844,7 +9844,7 @@ (define_insn "mve_vadciq_m_<supf>v4si"
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VADCIQ_M))
(set (reg:SI VFPCC_REGNUM)
(unspec:SI [(const_int 0)]
@@ -9880,7 +9880,7 @@ (define_insn "mve_vadcq_m_<supf>v4si"
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "0")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VADCQ_M))
(set (reg:SI VFPCC_REGNUM)
(unspec:SI [(reg:SI VFPCC_REGNUM)]
@@ -9917,7 +9917,7 @@ (define_insn "mve_vsbciq_m_<supf>v4si"
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VSBCIQ_M))
(set (reg:SI VFPCC_REGNUM)
(unspec:SI [(const_int 0)]
@@ -9953,7 +9953,7 @@ (define_insn "mve_vsbcq_m_<supf>v4si"
(unspec:V4SI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
(match_operand:V4SI 3 "s_register_operand" "w")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:V4BI 4 "vpr_register_operand" "Up")]
VSBCQ_M))
(set (reg:SI VFPCC_REGNUM)
(unspec:SI [(reg:SI VFPCC_REGNUM)]
@@ -10457,7 +10457,7 @@ (define_insn "arm_vcx1q<a>_p_v16qi"
(unspec:V16QI [(match_operand:SI 1 "const_int_coproc_operand" "i")
(match_operand:V16QI 2 "register_operand" "0")
(match_operand:SI 3 "const_int_mve_cde1_operand" "i")
- (match_operand:HI 4 "vpr_register_operand" "Up")]
+ (match_operand:V16BI 4 "vpr_register_operand" "Up")]
CDE_VCX))]
"TARGET_CDE && TARGET_HAVE_MVE"
"vpst\;vcx1<a>t\\tp%c1, %q0, #%c3"
@@ -10471,7 +10471,7 @@ (define_insn "arm_vcx2q<a>_p_v16qi"
(match_operand:V16QI 2 "register_operand" "0")
(match_operand:V16QI 3 "register_operand" "t")
(match_operand:SI 4 "const_int_mve_cde2_operand" "i")
- (match_operand:HI 5 "vpr_register_operand" "Up")]
+ (match_operand:V16BI 5 "vpr_register_operand" "Up")]
CDE_VCX))]
"TARGET_CDE && TARGET_HAVE_MVE"
"vpst\;vcx2<a>t\\tp%c1, %q0, %q3, #%c4"
@@ -10486,7 +10486,7 @@ (define_insn "arm_vcx3q<a>_p_v16qi"
(match_operand:V16QI 3 "register_operand" "t")
(match_operand:V16QI 4 "register_operand" "t")
(match_operand:SI 5 "const_int_mve_cde3_operand" "i")
- (match_operand:HI 6 "vpr_register_operand" "Up")]
+ (match_operand:V16BI 6 "vpr_register_operand" "Up")]
CDE_VCX))]
"TARGET_CDE && TARGET_HAVE_MVE"
"vpst\;vcx3<a>t\\tp%c1, %q0, %q3, %q4, #%c5"
--
2.25.1
next prev parent reply other threads:[~2022-01-13 15:01 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-13 14:56 [PATCH v3 00/15] ARM/MVE use vectors of boolean for predicates Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 01/15] arm: Add new tests for comparison vectorization with Neon and MVE Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 02/15] arm: Add tests for PR target/100757 Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 03/15] arm: Add tests for PR target/101325 Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 04/15] arm: Add GENERAL_AND_VPR_REGS regclass Christophe Lyon
2022-01-19 18:17 ` Andre Vieira (lists)
2022-01-20 9:14 ` Christophe Lyon
2022-01-20 9:43 ` Andre Vieira (lists)
2022-01-20 10:40 ` Richard Sandiford
2022-01-20 10:45 ` Andre Vieira (lists)
2022-01-27 16:21 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 05/15] arm: Add support for VPR_REG in arm_class_likely_spilled_p Christophe Lyon
2022-01-19 18:25 ` Andre Vieira (lists)
2022-01-20 9:20 ` Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 06/15] arm: Fix mve_vmvnq_n_<supf><mode> argument mode Christophe Lyon
2022-01-19 19:03 ` Andre Vieira (lists)
2022-01-20 9:23 ` Christophe Lyon
2022-01-20 9:38 ` Andre Simoes Dias Vieira
2022-01-20 9:44 ` Christophe Lyon
2022-01-20 10:45 ` Richard Sandiford
2022-01-20 11:06 ` Andre Vieira (lists)
2022-01-13 14:56 ` [PATCH v3 07/15] arm: Implement MVE predicates as vectors of booleans Christophe Lyon
2022-01-21 11:20 ` Andre Vieira (lists)
2022-01-21 22:30 ` Christophe Lyon
2022-01-27 16:28 ` Kyrylo Tkachov
2022-01-27 18:10 ` Christophe Lyon
2022-01-31 18:01 ` Richard Sandiford
2022-01-31 22:57 ` Christophe Lyon
2022-02-01 3:42 ` Richard Sandiford
2022-02-02 16:51 ` Christophe Lyon
2022-02-04 9:42 ` Richard Sandiford
2022-02-04 9:54 ` Richard Sandiford
2022-02-17 15:39 ` Christophe Lyon
2022-02-21 18:18 ` Richard Sandiford
2022-01-13 14:56 ` [PATCH v3 08/15] arm: Implement auto-vectorized MVE comparisons with vectors of boolean predicates Christophe Lyon
2022-01-27 16:37 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 09/15] arm: Fix vcond_mask expander for MVE (PR target/100757) Christophe Lyon
2022-01-27 16:55 ` Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 10/15] arm: Convert remaining MVE vcmp builtins to predicate qualifiers Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 11/15] arm: Convert more MVE " Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 12/15] arm: Convert more load/store " Christophe Lyon
2022-01-27 16:56 ` Kyrylo Tkachov
2022-01-13 14:56 ` Christophe Lyon [this message]
2022-01-27 16:56 ` [PATCH v3 13/15] arm: Convert more MVE/CDE " Kyrylo Tkachov
2022-01-13 14:56 ` [PATCH v3 14/15] arm: Add VPR_REG to ALL_REGS Christophe Lyon
2022-01-13 14:56 ` [PATCH v3 15/15] arm: Fix constraint check for V8HI in mve_vector_mem_operand Christophe Lyon
2022-01-14 17:03 ` [arm] MVE: Relax addressing modes for full loads and stores Andre Vieira (lists)
2022-01-17 7:48 ` Christophe Lyon
2022-03-07 14:16 ` Andre Vieira (lists)
2022-03-07 16:14 ` Kyrylo Tkachov
2022-01-14 13:18 ` [PATCH v3 00/15] ARM/MVE use vectors of boolean for predicates Christophe Lyon
2022-01-14 13:33 ` Richard Biener
2022-01-14 14:22 ` Kyrylo Tkachov
2022-01-26 8:40 ` Christophe Lyon
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