From: YunQiang Su <yunqiang.su@cipunited.com>
To: gcc-patches@gcc.gnu.org
Cc: macro@orcam.me.uk, YunQiang Su <yunqiang.su@cipunited.com>
Subject: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU
Date: Wed, 9 Feb 2022 03:18:37 +0000 [thread overview]
Message-ID: <20220209031837.3167330-1-yunqiang.su@cipunited.com> (raw)
In-Reply-To: <20220126032920.1608048-1-yunqiang.su@cipunited.com>
If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.
gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_prologue):
IPL is 8bit for MCU ASE.
---
gcc/config/mips/mips.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..d823c459b75 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
if (!cfun->machine->keep_interrupts_masked_p
&& cfun->machine->int_mask == INT_MASK_EIC)
emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
- GEN_INT (6),
+ TARGET_MCU ? GEN_INT (8) : GEN_INT (6),
GEN_INT (SR_IPL),
gen_rtx_REG (SImode, K0_REG_NUM)));
--
2.30.2
next prev parent reply other threads:[~2022-02-09 3:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 3:29 [PATCH] MIPS: use 8bit for IPL in Cause register YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki
2022-02-09 3:18 ` YunQiang Su [this message]
2022-02-12 3:54 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU Jeff Law
2022-02-12 8:47 ` Maciej W. Rozycki
2022-03-15 7:00 ` YunQiang Su
2022-03-15 6:51 ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41 ` Maciej W. Rozycki
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