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From: shihua@iscas.ac.cn
To: gcc-patches@gcc.gnu.org
Cc: ben.marshall@pqshield.com, kito.cheng@sifive.com,
	cmuellner@ventanamicro.com, palmer@dabbelt.com,
	andrew@sifive.com, lazyparser@gmail.com, jiawei@iscas.ac.cn,
	mjos@iki.fi, LiaoShihua <shihua@iscas.ac.cn>
Subject: [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros for Crypto extension
Date: Wed, 23 Feb 2022 17:44:18 +0800	[thread overview]
Message-ID: <20220223094418.3518-6-shihua@iscas.ac.cn> (raw)
In-Reply-To: <20220223094418.3518-1-shihua@iscas.ac.cn>

From: LiaoShihua <shihua@iscas.ac.cn>

gcc/ChangeLog:

        * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):Add __riscv_zks, __riscv_zk, __riscv_zkn

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/predef-17.c: New test.

---
 gcc/config/riscv/riscv-c.cc                |  9 ++++
 gcc/testsuite/gcc.target/riscv/predef-17.c | 59 ++++++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-17.c

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 73c62f41274..d6c153e8d7c 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -63,6 +63,15 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
       builtin_define ("__riscv_fdiv");
       builtin_define ("__riscv_fsqrt");
     }
+  
+  if (TARGET_ZBKB && TARGET_ZBKC && TARGET_ZBKX && TARGET_ZKNE && TARGET_ZKND && TARGET_ZKNH)
+    {
+      builtin_define ("__riscv_zk");
+      builtin_define ("__riscv_zkn");
+    }
+
+  if (TARGET_ZBKB && TARGET_ZBKC && TARGET_ZBKX && TARGET_ZKSED && TARGET_ZKSH)
+      builtin_define ("__riscv_zks");
 
   switch (riscv_abi)
     {
diff --git a/gcc/testsuite/gcc.target/riscv/predef-17.c b/gcc/testsuite/gcc.target/riscv/predef-17.c
new file mode 100644
index 00000000000..4366dee1016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-17.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_zk)
+#error "__riscv_zk"
+#endif
+
+#if !defined(__riscv_zkn)
+#error "__riscv_zkn"
+#endif
+
+#if !defined(__riscv_zks)
+#error "__riscv_zks"
+#endif
+
+#if !defined(__riscv_zbkb)
+#error "__riscv_zbkb"
+#endif
+
+#if !defined(__riscv_zbkc)
+#error "__riscv_zbkc"
+#endif
+
+#if !defined(__riscv_zbkx)
+#error "__riscv_zbkx"
+#endif
+
+#if !defined(__riscv_zknd)
+#error "__riscv_zknd"
+#endif
+
+#if !defined(__riscv_zkne)
+#error "__riscv_zkne"
+#endif
+
+#if !defined(__riscv_zknh)
+#error "__riscv_zknh"
+#endif
+
+#if !defined(__riscv_zksh)
+#error "__riscv_zksh"
+#endif
+
+  return 0;
+}
\ No newline at end of file
-- 
2.31.1.windows.1


  parent reply	other threads:[~2022-02-23  9:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-23  9:44 [PATCH 0/5 V1] RISC-V:Implement Crypto extension's instruction patterns and it's intrinsics shihua
2022-02-23  9:44 ` [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension shihua
2022-02-28 16:04   ` Kito Cheng
2022-02-23  9:44 ` [PATCH 2/5 V1] RISC-V:Implement built-in instructions " shihua
2022-02-23  9:44 ` [PATCH 3/5 V1] RISC-V:Implement intrinsics " shihua
2022-02-28 15:34   ` Kito Cheng
2022-02-23  9:44 ` [PATCH 4/5 V1] RISC-V:Implement testcases " shihua
2022-03-01 13:00   ` Kito Cheng
2022-03-01 13:49     ` Kito Cheng
2022-02-23  9:44 ` shihua [this message]
2022-02-24  9:55   ` [PATCH 5/5 V1] RISC-V:Implement architecture extension test macros " Kito Cheng
2022-02-28 15:56     ` Kito Cheng

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