From: Patrick O'Neill <patrick@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, dlustig@nvidia.com,
kito.cheng@sifive.com, palmer@rivosinc.com, vineetg@rivosinc.com,
andrew@sifive.com, Patrick O'Neill <patrick@rivosinc.com>
Subject: [RFC 1/7] RISCV: Enforce Libatomic LR/SC SEQ_CST
Date: Thu, 7 Apr 2022 11:33:45 -0700 [thread overview]
Message-ID: <20220407183351.295188-2-patrick@rivosinc.com> (raw)
In-Reply-To: <20220407183351.295188-1-patrick@rivosinc.com>
Replace LR.aq/SC.rl pairs with the SEQ_CST LR.aqrl/SC.rl pairs
recommended by table A.6 of the ISA manual.
2022-03-31 Patrick O'Neill <patrick@rivosinc.com>
* atomic.c: Change LR.aq/SC.rl pairs into sequentially
consistent LR.aqrl/SC.rl pair.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
libgcc/config/riscv/atomic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/libgcc/config/riscv/atomic.c b/libgcc/config/riscv/atomic.c
index 7007e7a20e4..834d0d4380e 100644
--- a/libgcc/config/riscv/atomic.c
+++ b/libgcc/config/riscv/atomic.c
@@ -39,7 +39,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
unsigned old, tmp1, tmp2; \
\
asm volatile ("1:\n\t" \
- "lr.w.aq %[old], %[mem]\n\t" \
+ "lr.w.aqrl %[old], %[mem]\n\t" \
#insn " %[tmp1], %[old], %[value]\n\t" \
invert \
"and %[tmp1], %[tmp1], %[mask]\n\t" \
@@ -73,7 +73,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
unsigned old, tmp1; \
\
asm volatile ("1:\n\t" \
- "lr.w.aq %[old], %[mem]\n\t" \
+ "lr.w.aqrl %[old], %[mem]\n\t" \
"and %[tmp1], %[old], %[mask]\n\t" \
"bne %[tmp1], %[o], 1f\n\t" \
"and %[tmp1], %[old], %[not_mask]\n\t" \
--
2.25.1
next prev parent reply other threads:[~2022-04-07 18:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 18:33 [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2022-04-07 18:33 ` Patrick O'Neill [this message]
2022-04-07 18:33 ` [RFC 2/7] RISCV: Enforce Atomic Compare Exchange SEQ_CST Patrick O'Neill
2022-04-07 18:33 ` [RFC 3/7] RISCV: Add AMO release bits Patrick O'Neill
2022-04-07 18:33 ` [RFC 4/7] RISCV: Optimize AMO Ops Patrick O'Neill
2022-04-07 18:33 ` [RFC 5/7] RISCV: Optimize LR/SC Pairs Patrick O'Neill
2022-04-07 18:33 ` [RFC 6/7] RISCV: Optimize Atomic Stores Patrick O'Neill
2022-04-07 18:33 ` [RFC 7/7] RISCV: Relax mem_thread_fence Patrick O'Neill
2022-05-10 0:52 ` [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
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