From: Patrick O'Neill <patrick@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, dlustig@nvidia.com,
kito.cheng@sifive.com, palmer@rivosinc.com, vineetg@rivosinc.com,
andrew@sifive.com, Patrick O'Neill <patrick@rivosinc.com>
Subject: [RFC 3/7] RISCV: Add AMO release bits
Date: Thu, 7 Apr 2022 11:33:47 -0700 [thread overview]
Message-ID: <20220407183351.295188-4-patrick@rivosinc.com> (raw)
In-Reply-To: <20220407183351.295188-1-patrick@rivosinc.com>
This patch sets the relevant .rl bits on amo operations.
2022-03-31 Patrick O'Neill <patrick@rivosinc.com>
* riscv.cc (riscv_print_operand): change behavior of %A to
include release bits.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
gcc/config/riscv/riscv.cc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..813e771bec7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3652,8 +3652,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
break;
case 'A':
- if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
+ if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)) &&
+ riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+ fputs (".aqrl", file);
+ else if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
fputs (".aq", file);
+ else if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+ fputs (".rl", file);
break;
case 'F':
--
2.25.1
next prev parent reply other threads:[~2022-04-07 18:34 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 18:33 [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
2022-04-07 18:33 ` [RFC 1/7] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2022-04-07 18:33 ` [RFC 2/7] RISCV: Enforce Atomic Compare Exchange SEQ_CST Patrick O'Neill
2022-04-07 18:33 ` Patrick O'Neill [this message]
2022-04-07 18:33 ` [RFC 4/7] RISCV: Optimize AMO Ops Patrick O'Neill
2022-04-07 18:33 ` [RFC 5/7] RISCV: Optimize LR/SC Pairs Patrick O'Neill
2022-04-07 18:33 ` [RFC 6/7] RISCV: Optimize Atomic Stores Patrick O'Neill
2022-04-07 18:33 ` [RFC 7/7] RISCV: Relax mem_thread_fence Patrick O'Neill
2022-05-10 0:52 ` [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings Patrick O'Neill
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