From: Segher Boessenkool <segher@kernel.crashing.org>
To: "Kewen.Lin" <linkw@linux.ibm.com>
Cc: Jakub Jelinek <jakub@redhat.com>,
Bill Schmidt <wschmidt@linux.ibm.com>,
Peter Bergner <bergner@linux.ibm.com>,
GCC Patches <gcc-patches@gcc.gnu.org>,
David Edelsohn <dje.gcc@gmail.com>
Subject: Re: [PATCH] rs6000: Guard bifs {un, }pack_{longdouble, ibm128} under hard float [PR103623]
Date: Mon, 11 Apr 2022 10:42:14 -0500 [thread overview]
Message-ID: <20220411154214.GW614@gate.crashing.org> (raw)
In-Reply-To: <31b02ece-83e3-f940-8898-c0a9c19c38bd@linux.ibm.com>
Hi!
On Mon, Apr 11, 2022 at 04:29:40PM +0800, Kewen.Lin wrote:
> on 2022/4/9 1:31 AM, Segher Boessenkool wrote:
> > On Fri, Apr 08, 2022 at 10:09:44AM +0800, Kewen.Lin wrote:
> > For me it fails during combine: the unspec suddenly doesn't recog
> > anymore. That might be that "d" thing yes, that is problematical.
> >
>
> I must miss something, I found in combine pass we still have the
> the insn_code unpacktf_nodm (recog-ed).
That is recognised many passes earlier though. When combine runs it
will ICE because recog failed (for powerpc64-linux anyway, everything
default, no -mcpu= etc.).
> > Or, try this patch?
> >
> > ===
> > diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> > index fdfbc6566a5c..f05b8358ba0a 100644
> > --- a/gcc/config/rs6000/rs6000.md
> > +++ b/gcc/config/rs6000/rs6000.md
> > @@ -14580,10 +14580,10 @@ (define_insn_and_split "unpack<mode>_dm"
> > [(set_attr "type" "fp,fpstore,mtvsr,mfvsr,store")])
> >
> > (define_insn_and_split "unpack<mode>_nodm"
> > - [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
> > + [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,m")
> > (unspec:<FP128_64>
> > - [(match_operand:FMOVE128 1 "register_operand" "d,d")
> > - (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
> > + [(match_operand:FMOVE128 1 "register_operand" "d,d,r")
> > + (match_operand:QI 2 "const_0_to_1_operand" "i,i,i")]
> > UNSPEC_UNPACK_128BIT))]
> > "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)"
> > "#"
> > @@ -14600,7 +14600,7 @@ (define_insn_and_split "unpack<mode>_nodm"
> >
> > operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
> > }
> > - [(set_attr "type" "fp,fpstore")])
> > + [(set_attr "type" "fp,fpstore,store")])
> >
> > (define_insn_and_split "pack<mode>"
> > [(set (match_operand:FMOVE128 0 "register_operand" "=&d")
> > ===
> >
> >
>
> Nice, I confirmed this makes ICE gone, I've filed one new PR
> PR105213 for GCC13 further tracking by associating this patch there.
Cool, I'll commit it later today then (after a final regstrap). The
_nodm pattern just missed the alternative for no FP regs (the _dm
pattern has it, so just an oversight).
Segher
next prev parent reply other threads:[~2022-04-11 15:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 2:11 [PATCH] rs6000: Guard bifs {un,}pack_{longdouble,ibm128} " Kewen.Lin
2022-03-15 11:36 ` PING^1 [PATCH] rs6000: Guard bifs {un, }pack_{longdouble, ibm128} " Kewen.Lin
2022-04-07 11:09 ` Segher Boessenkool
2022-04-07 13:00 ` Jakub Jelinek
2022-04-08 2:09 ` Kewen.Lin
2022-04-08 17:31 ` Segher Boessenkool
2022-04-11 8:29 ` Kewen.Lin
2022-04-11 15:42 ` Segher Boessenkool [this message]
2022-04-12 2:02 ` Kewen.Lin
2022-04-12 19:11 ` Segher Boessenkool
2022-04-13 1:05 ` Kewen.Lin
2022-04-08 16:56 ` Segher Boessenkool
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