From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id C907E3858C50 for ; Thu, 5 May 2022 14:35:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C907E3858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 245EX9ni025618; Thu, 5 May 2022 09:33:09 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 245EX8mR025609; Thu, 5 May 2022 09:33:08 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Thu, 5 May 2022 09:33:08 -0500 From: Segher Boessenkool To: Alexandre Oliva Cc: gcc-patches@gcc.gnu.org, ebotcazou@libertysurf.fr, vmakarov@redhat.com, dje.gcc@gmail.com Subject: Re: [PATCH] [PR100106] Reject unaligned subregs when strict alignment is required Message-ID: <20220505143308.GC25951@gate.crashing.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 May 2022 14:35:20 -0000 On Thu, May 05, 2022 at 03:52:01AM -0300, Alexandre Oliva wrote: > The testcase for pr100106, compiled with optimization for 32-bit > powerpc -mcpu=604 with -mstrict-align expands the initialization of a > union from a float _Complex value into a load from an SCmode > constant pool entry, aligned to 4 bytes, into a DImode pseudo, > requiring 8-byte alignment. > + else if (reg && MEM_P (reg) > + && STRICT_ALIGNMENT && MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (omode)) > + return false; Please fix the line breaks? Either do a break before every &&, or put as many things as possible on one line? Note that you should never have paradoxical subregs of mem on rs6000 or any other target with INSN_SCHEDULING. > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/pr100106-sa.c > @@ -0,0 +1,4 @@ > +/* { dg-do compile { target { ilp32 } } } */ > +/* { dg-options "-mcpu=604 -O -mstrict-align" } */ > + > +#include "../../gcc.c-torture/compile/pr100106.c" It is better to copy the 11 lines of code. Please comment what the ilp32 is for (namely, the -mcpu= will barf without it).. The testcase is okay with those changes, thanks! Seghr