From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 9BD4F38485AD for ; Tue, 10 May 2022 03:25:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9BD4F38485AD Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-01 (Coremail) with SMTP id qwCowAAHnhU323lioBtBBQ--.37585S3; Tue, 10 May 2022 11:25:49 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: andrew@sifive.com, palmer@dabbelt.com, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, yulong Subject: [PATCH V4 1/3] RISC-V: Add mininal support for Zicbo[mzp] Date: Tue, 10 May 2022 11:25:24 +0800 Message-Id: <20220510032526.11560-2-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn> References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowAAHnhU323lioBtBBQ--.37585S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAFW7uF47tF45Wr4DJFW7twb_yoW5ur1xpF 4kW39Ivw1FqrsxWw4xtw1rW345A3ZYgr1rCr4ru34UA3yDXrWkAF1q9w13Zr4kXFZ8Zr92 v3WY93909a1UCa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBq14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lw4CEc2x0rVAKj4xxMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjKL9UUUUUU== X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 May 2022 03:25:56 -0000 From: yulong This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. (MASK_ZICBOM): New. (MASK_ZICBOP): New. (TARGET_ZICBOZ): New. (TARGET_ZICBOM): New. (TARGET_ZICBOP): New. * config/riscv/riscv.opt: New. --- gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ gcc/config/riscv/riscv-opts.h | 8 ++++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 19 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 1501242e296..bf7a7caabef 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -165,6 +165,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, + {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 15bb5e76854..1e153b3a6e7 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -145,6 +145,14 @@ enum stack_protector_guard { #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) +#define MASK_ZICBOZ (1 << 0) +#define MASK_ZICBOM (1 << 1) +#define MASK_ZICBOP (1 << 2) + +#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0) +#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) +#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) + /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to caclulate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 492aad12324..d1b3c1840a6 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -209,6 +209,9 @@ int riscv_vector_elen_flags TargetVariable int riscv_zvl_flags +TargetVariable +int riscv_zicmo_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): -- 2.17.1