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From: Richard Earnshaw <rearnsha@arm.com>
To: gcc-patches@gcc.gnu.org
Cc: Richard Earnshaw <rearnsha@arm.com>
Subject: [committed 1/2] arm: fix some issues in mve_vector_mem_operand
Date: Fri, 13 May 2022 11:28:07 +0100	[thread overview]
Message-ID: <20220513102808.3092726-1-rearnsha@arm.com> (raw)

[-- Attachment #1: Type: text/plain, Size: 512 bytes --]


There are a couple of issues with the mve_vector_mem_operand function.
Firstly, SP is permitted as a register provided there is no write-back
operation.  Secondly, there were some cases where 'strict' was not
being applied when checking which registers had been used.

gcc/ChangeLog:

	* config/arm/arm.cc (mve_vector_mem_operand): Allow SP_REGNUM
	when there is no write-back.  Fix use when strict is true.
---
 gcc/config/arm/arm.cc | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)


[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-arm-fix-some-issues-in-mve_vector_mem_operand.patch --]
[-- Type: text/x-patch; name="0001-arm-fix-some-issues-in-mve_vector_mem_operand.patch", Size: 1851 bytes --]

diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc
index 69a18c2f157..2afe0445ed5 100644
--- a/gcc/config/arm/arm.cc
+++ b/gcc/config/arm/arm.cc
@@ -13527,7 +13527,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict)
       int reg_no = REGNO (op);
       return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode)
 	       ? reg_no <= LAST_LO_REGNUM
-	       :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM))
+	       : reg_no < LAST_ARM_REGNUM)
 	      || (!strict && reg_no >= FIRST_PSEUDO_REGISTER));
     }
   code = GET_CODE (op);
@@ -13536,10 +13536,10 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict)
       || code == PRE_INC || code == POST_DEC)
     {
       reg_no = REGNO (XEXP (op, 0));
-      return ((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode)
-	      ? reg_no <= LAST_LO_REGNUM
-	      :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM))
-	|| reg_no >= FIRST_PSEUDO_REGISTER;
+      return (((mode == E_V8QImode || mode == E_V4QImode || mode == E_V4HImode)
+	       ? reg_no <= LAST_LO_REGNUM
+	       :(reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM))
+	      || (!strict && reg_no >= FIRST_PSEUDO_REGISTER));
     }
   else if (((code == POST_MODIFY || code == PRE_MODIFY)
 	    && GET_CODE (XEXP (op, 1)) == PLUS
@@ -13580,10 +13580,11 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict)
 	  default:
 	    return FALSE;
 	}
-      return reg_no >= FIRST_PSEUDO_REGISTER
-	|| (MVE_STN_LDW_MODE (mode)
-	    ? reg_no <= LAST_LO_REGNUM
-	    : (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM));
+      return ((!strict && reg_no >= FIRST_PSEUDO_REGISTER)
+	      || (MVE_STN_LDW_MODE (mode)
+		  ? reg_no <= LAST_LO_REGNUM
+		  : (reg_no < LAST_ARM_REGNUM
+		     && (code == PLUS || reg_no != SP_REGNUM))));
     }
   return FALSE;
 }

             reply	other threads:[~2022-05-13 10:28 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13 10:28 Richard Earnshaw [this message]
2022-05-13 10:28 ` [committed 2/2] arm: correctly handle misaligned MEMs on MVE [PR105463] Richard Earnshaw

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