From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by sourceware.org (Postfix) with ESMTPS id 46217382D465; Fri, 27 May 2022 06:07:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 46217382D465 Received: by mail-wr1-f49.google.com with SMTP id t13so4520847wrg.9; Thu, 26 May 2022 23:07:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7BX/EJSHZDmG5rSofzX3aRFdnslKz9EPtSiUyYx4loI=; b=r59SrZ+Uz1MIBKVHhWSl1Ip180KXeezJEEd3fAoFWFMPfkeN5QgLJ5SWMQVmoj9+e0 w/Wr8QzwamDx65lZFpeAk1kyxIswe1oS0qp2Cjwv2/UOZlTbqCAi3t0Q4hKSohgLiiXv gMiwbJ9KRG8ZzCCPXtk24t8pKQJCzpX2VGj/4Iczdvh0mXMPHhFj6S43irvdHXnnO/fe 6DlfWWfFBJ4QTDzhL9YE8HcjIjXVZIbkOyYmfyMriWiQ07I6szyN0rYg18VsmEZnpUYo Jv8owrsVRLP16qeAp7fa8zU2qOed0mwri3LjEyyiPrx6XcBBtT8ZgiE6PQafV4kuvmOu 3Ljg== X-Gm-Message-State: AOAM5329fTZHP3JBUj1Uah0scBe1QESSmwpg3uOg9+i4QFgtVkWkHWum /5NK0BvuNrFWkcamFYui9MWL1SNH1HfmQnh3 X-Google-Smtp-Source: ABdhPJwuPWU/TFj04FI9a13x5vGtsQ42O1rpgwS3aHULiv8dYUsmJxSwIEY5RoBrJ99qmfucaLGosA== X-Received: by 2002:a5d:4e82:0:b0:210:dd9:a665 with SMTP id e2-20020a5d4e82000000b002100dd9a665mr4518066wru.656.1653631650042; Thu, 26 May 2022 23:07:30 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:29 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 3/9] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] Date: Fri, 27 May 2022 08:07:17 +0200 Message-Id: <20220527060723.235095-4-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 May 2022 06:07:32 -0000 A previous patch took care, that the proper memory ordering suffixes for AMOs are emitted. Therefore there is no reason to keep the fence generation mechanism for release operations. gcc/ PR 100265 * config/riscv/riscv.c (riscv_memmodel_needs_release_fence): Remove function. * config/riscv/riscv.c (riscv_print_operand): Remove %F format specifier. * config/riscv/sync.md: Remove %F format specifier uses. --- gcc/config/riscv/riscv.cc | 29 ----------------------------- gcc/config/riscv/sync.md | 16 ++++++++-------- 2 files changed, 8 insertions(+), 37 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 983a567c69c..5bb22044ce9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3599,29 +3599,6 @@ riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model) } } -/* Return true if a FENCE should be emitted to before a memory access to - implement the release portion of memory model MODEL. */ - -static bool -riscv_memmodel_needs_release_fence (const enum memmodel model) -{ - switch (model) - { - case MEMMODEL_ACQ_REL: - case MEMMODEL_SEQ_CST: - case MEMMODEL_RELEASE: - return true; - - case MEMMODEL_ACQUIRE: - case MEMMODEL_CONSUME: - case MEMMODEL_RELAXED: - return false; - - default: - gcc_unreachable (); - } -} - /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping @@ -3629,7 +3606,6 @@ riscv_memmodel_needs_release_fence (const enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. - 'F' Print a FENCE if the memory model requires a release. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -3663,11 +3639,6 @@ riscv_print_operand (FILE *file, rtx op, int letter) riscv_print_amo_memory_ordering_suffix (file, model); break; - case 'F': - if (riscv_memmodel_needs_release_fence (model)) - fputs ("fence iorw,ow; ", file); - break; - case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 86b41e6b00a..ddaeda0116d 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -65,7 +65,7 @@ (define_insn "atomic_store" (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_ATOMIC_STORE))] "TARGET_ATOMIC" - "%F2amoswap.%A2 zero,%z1,%0" + "amoswap.%A2 zero,%z1,%0" [(set (attr "length") (const_int 8))]) (define_insn "atomic_" @@ -76,8 +76,8 @@ (define_insn "atomic_" (match_operand:SI 2 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F2amo.%A2 zero,%z1,%0" - [(set (attr "length") (const_int 8))]) + "amo.%A2 zero,%z1,%0" +) (define_insn "atomic_fetch_" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -89,8 +89,8 @@ (define_insn "atomic_fetch_" (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP))] "TARGET_ATOMIC" - "%F3amo.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amo.%A3 %0,%z2,%1" +) (define_insn "atomic_exchange" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -101,8 +101,8 @@ (define_insn "atomic_exchange" (set (match_dup 1) (match_operand:GPR 2 "register_operand" "0"))] "TARGET_ATOMIC" - "%F3amoswap.%A3 %0,%z2,%1" - [(set (attr "length") (const_int 8))]) + "amoswap.%A3 %0,%z2,%1" +) (define_insn "atomic_cas_value_strong" [(set (match_operand:GPR 0 "register_operand" "=&r") @@ -115,7 +115,7 @@ (define_insn "atomic_cas_value_strong" UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" - "%F5 1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" + "1: lr.%A5 %0,%1; bne %0,%z2,1f; sc.%A4 %6,%z3,%1; bnez %6,1b; 1:" [(set (attr "length") (const_int 20))]) (define_expand "atomic_compare_and_swap" -- 2.35.3