From: Christoph Muellner <cmuellner@gcc.gnu.org>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Aaron Durbin <adurbin@rivosinc.com>,
Patrick O'Neill <patrick@rivosinc.com>,
Vineet Gupta <vineetg@rivosinc.com>
Subject: [PATCH v3 5/9] RISC-V: Emit fences according to chosen memory model [PR 100265]
Date: Fri, 27 May 2022 08:07:19 +0200 [thread overview]
Message-ID: <20220527060723.235095-6-cmuellner@gcc.gnu.org> (raw)
In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org>
mem_thread_fence gets the desired memory model as operand.
Let's emit fences according to this value (as defined in section
"Code Porting and Mapping Guidelines" of the unpriv spec).
gcc/
PR 100265
* config/riscv/sync.md (mem_thread_fence):
Emit fences according to given operand.
* config/riscv/sync.md (mem_fence):
Add INSNs for different fence flavours.
* config/riscv/sync.md (mem_thread_fence_1):
Remove.
---
gcc/config/riscv/sync.md | 41 +++++++++++++++++++++++++++-------------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 86f4cef6af9..ae80f94f2e0 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -34,26 +34,41 @@ (define_code_attr atomic_optab
;; Memory barriers.
(define_expand "mem_thread_fence"
- [(match_operand:SI 0 "const_int_operand" "")] ;; model
+ [(match_operand:SI 0 "const_int_operand")] ;; model
""
{
- if (INTVAL (operands[0]) != MEMMODEL_RELAXED)
- {
- rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (mem) = 1;
- emit_insn (gen_mem_thread_fence_1 (mem, operands[0]));
- }
+ enum memmodel model = memmodel_from_int (INTVAL (operands[0]));
+ if (!(is_mm_relaxed (model)))
+ emit_insn (gen_mem_fence (operands[0]));
DONE;
})
-;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
-;; conservatively emit a full FENCE.
-(define_insn "mem_thread_fence_1"
+(define_expand "mem_fence"
+ [(set (match_dup 1)
+ (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
+ UNSPEC_MEMORY_BARRIER))]
+ ""
+{
+ operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[1]) = 1;
+})
+
+(define_insn "*mem_fence"
[(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
- (match_operand:SI 1 "const_int_operand" "")] ;; model
+ (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
+ UNSPEC_MEMORY_BARRIER))]
""
- "fence\tiorw,iorw")
+{
+ enum memmodel model = memmodel_from_int (INTVAL (operands[1]));
+ if (is_mm_consume (model) || is_mm_acquire (model))
+ return "fence\tr, rw";
+ else if (is_mm_release (model))
+ return "fence\trw, w";
+ else if (is_mm_acq_rel (model))
+ return "fence.tso";
+ else
+ return "fence\trw, rw";
+})
;; Atomic memory operations.
--
2.35.3
next prev parent reply other threads:[~2022-05-27 6:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-27 6:07 [PATCH v3 0/9] [RISC-V] Atomics improvements Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 1/9] RISC-V: Simplify memory model code [PR 100265] Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 2/9] RISC-V: Emit proper memory ordering suffixes for AMOs " Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 3/9] RISC-V: Eliminate %F specifier from riscv_print_operand() " Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 4/9] RISC-V: Use STORE instead of AMOSWAP for atomic stores " Christoph Muellner
2022-05-27 6:07 ` Christoph Muellner [this message]
2022-05-27 6:07 ` [PATCH v3 6/9] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 7/9] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 8/9] RISC-V: Add s.ext-consuming " Christoph Muellner
2022-05-27 6:07 ` [PATCH v3 9/9] RISC-V: Introduce predicate "riscv_sync_memory_operand" " Christoph Muellner
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