From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by sourceware.org (Postfix) with ESMTPS id 34AE5382D46F; Fri, 27 May 2022 06:07:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 34AE5382D46F Received: by mail-wm1-f53.google.com with SMTP id d5-20020a05600c34c500b0039776acee62so1710006wmq.1; Thu, 26 May 2022 23:07:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jxU8rJAqOOf63y9+pJES4cMWcxe+Iutbv9QGdeboVdY=; b=1gc3iJVbMk6G9ucuqbENPNgoDq3eN679yxC/+GfkisCVUGLYZAeSMkUStnY9fNYsq1 VIoqKr3OJJ+xIxlp5f+ujfK1WPfwK6J4NTYSRyuZlk/bwqolpFPR47bHQLlmteA0Mrq6 2oKgTLEh43b5mfMniChVy0zE5wGxy0IYVLSLfbu84HhwPqRRpBgMpliwFkWSvWjs+ICf Yc0AXlcDDD+iE2W7ISpD5GUPjnREX7Q1JD+u6qC+aiZ+1mYyM+YMUM12VYgBbLEa3sI7 GHSEtxu2tSqyejikviLJZIywQ7KqwS+3Z9IJyXDYfeHAoKEjUa16LfWY2J3vqrzK0it6 kuBg== X-Gm-Message-State: AOAM5334/ImLx78n2g7TETd3Q2SqGBiMcZXaO6Wkmnm+/G4Q70cPVQGp SgB8x+t9Ip8RHkQBwEISKRfeK6WYwJDXq9lz X-Google-Smtp-Source: ABdhPJxn1ZZqdHw/ErDEVUxQ+fs9aKmIMpWGR2xwyUAK1gSAej4of6ciqCR0N9GkMfU3MUqSvrtedw== X-Received: by 2002:a1c:2504:0:b0:397:288c:c58b with SMTP id l4-20020a1c2504000000b00397288cc58bmr5406200wml.53.1653631654932; Thu, 26 May 2022 23:07:34 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id t125-20020a1c4683000000b00395f15d993fsm1169860wma.5.2022.05.26.23.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 23:07:34 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner , Aaron Durbin , Patrick O'Neill , Vineet Gupta Subject: [PATCH v3 7/9] RISC-V: Model INSNs for LR and SC [PR 100266] Date: Fri, 27 May 2022 08:07:21 +0200 Message-Id: <20220527060723.235095-8-cmuellner@gcc.gnu.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220527060723.235095-1-cmuellner@gcc.gnu.org> References: <20220527060723.235095-1-cmuellner@gcc.gnu.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_MANYTO, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 May 2022 06:07:37 -0000 In order to emit LR/SC sequences, let's provide INSNs, which take care of memory ordering constraints. gcc/ PR 100266 * config/rsicv/sync.md (UNSPEC_LOAD_RESERVED): New. * config/rsicv/sync.md (UNSPEC_STORE_CONDITIONAL): New. * config/riscv/sync.md (riscv_load_reserved): New. * config/riscv/sync.md (riscv_store_conditional): New. --- gcc/config/riscv/sync.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 9eb0dde9086..3494683947e 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,8 @@ (define_c_enum "unspec" [ UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER + UNSPEC_LOAD_RESERVED + UNSPEC_STORE_CONDITIONAL ]) (define_code_iterator any_atomic [plus ior xor and]) @@ -113,6 +115,28 @@ (define_expand "atomic_store" DONE; }) +(define_insn "@riscv_load_reserved" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_LOAD_RESERVED))] + "TARGET_ATOMIC" + "lr.%A2 %0, %1" +) + +(define_insn "@riscv_store_conditional" + [(set (match_operand:GPR 0 "register_operand" "=&r") + (unspec_volatile:GPR [(const_int 0)] UNSPEC_STORE_CONDITIONAL)) + (set (match_operand:GPR 1 "memory_operand" "=A") + (unspec_volatile:GPR + [(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:SI 3 "const_int_operand")] ;; model + UNSPEC_STORE_CONDITIONAL))] + "TARGET_ATOMIC" + "sc.%A3 %0, %z2, %1" +) + (define_insn "atomic_" [(set (match_operand:GPR 0 "memory_operand" "+A") (unspec_volatile:GPR -- 2.35.3