From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai
Subject: [PATCH 00/21] *** Add RVV (RISC-V 'V' Extension) support ***
Date: Tue, 31 May 2022 16:49:51 +0800 [thread overview]
Message-ID: <20220531085012.269719-1-juzhe.zhong@rivai.ai> (raw)
From: zhongjuzhe <juzhe.zhong@rivai.ai>
Hello, since our RVV GCC has open source in RISC-V foundation repo:
https://github.com/riscv-collab/riscv-gcc/tree/riscv-gcc-rvv-next which
has been widely used by different users. During this time, I have polished
the codes and fixed bugs for different users. So I think it's ready to
push them to GCC upstream.
This patch supports RVV intrinsics including C and C++ api which
is documented here:https://github.com/riscv-non-isa/rvv-intrinsic-doc.
FP16 and segment RVV intrinsics are not included in this patch:
Because there is no FP16 (ZFH extension) support on GCC upstream, I didn't
including RVV with FP16 in this patch. I will support in the next patch.
Because segment support needs some modification on the codes that doesn't belong to
RISC-V port, I didn't including them in this patch. I will support in the next patch.
Auto-vectorization is not supported in this patch. It will be supported in the future.
The vsetvl support for each RVV intrinsic is gcc/config/riscv/riscv-insert-vsetvl.cc.
The pass implementation reference LLVM: https://github.com/llvm/llvm-project/commits/main/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp.
They are almost totally same.
The SEW=64 handling on RV32 system:
Example:
vuint64m8_t
foo (vuint64m8_t op1, int64_t r, size_t vl)
{
return vadd_vx_u64m8(op1, r, vl);
}
ASM:
foo:
vsetvli a5,zero,e32,m1,ta,mu
li a5,1431654400
addi a5,a5,1365
vmv.v.x v0,a5
vsetvli a5,zero,e32,m8,ta,mu
vmv.v.x v24,a1
vmerge.vxm v24,v24,a0,v0
vsetvli zero,a2,e64,m8,ta,mu
vadd.vv v8,v8,v24
ret
The 'v0' is the mask with all bits as 0b010101010101010.... duplicate '01' mask.
We first move the high-32bit into the vector. And second merge the low-32bit into
vector with mask (0b0101010101010101010101010101......). Then we can get the duplicated
vector.
LLVM uses two 32bit scalar store and then use vlse instruction to get the duplicated
vector. This way need to access memory and I have tried this method in GCC, the codegen
is bad. So I implement the handling SEW=64 on RV32 system as descibed before. This can
be optimized in the future.
*** BLURB HERE ***
zhongjuzhe (21):
Add RVV modes and support scalable vector
Add RVV intrinsic framework
Add RVV datatypes
Add RVV intrinsic enable #pragma riscv intrinsic "vector" and
introduce RVV header "riscv_vector.h"
Add RVV configuration intrinsic
Add insert-vsetvl pass
Add register spilling support
Add poly manipulation
Add misc function intrinsic support
Add unit-stride load store intrinsics
Add calling function support
Add set get intrinsic support
Adjust scalable frame and full testcases
Add load and store intrinsics
Add integer intrinsics
Add integer intrinsic C api testcases
Add integer intrinsic C++ api testcases
Add rest intrinsic support
Add rest C api intrinsic testcases
Add rest C++ intrinsic api testcases
Add SEW=64 on RV32 system testcases
gcc/config.gcc | 6 +-
gcc/config/riscv/constraints.md | 47 +
gcc/config/riscv/md-parser | 205 +
gcc/config/riscv/predicates.md | 98 +-
gcc/config/riscv/riscv-builtins.cc | 88 +-
gcc/config/riscv/riscv-c.cc | 65 +
gcc/config/riscv/riscv-insert-vsetvl.cc | 2312 +
gcc/config/riscv/riscv-modes.def | 177 +
gcc/config/riscv/riscv-opts.h | 39 +
gcc/config/riscv/riscv-passes.def | 2 +
gcc/config/riscv/riscv-protos.h | 81 +-
gcc/config/riscv/riscv-sr.cc | 2 +-
.../riscv/riscv-vector-builtins-functions.cc | 4788 ++
.../riscv/riscv-vector-builtins-functions.def | 391 +
.../riscv/riscv-vector-builtins-functions.h | 2905 +
.../riscv/riscv-vector-builtins-iterators.def | 819 +
gcc/config/riscv/riscv-vector-builtins.cc | 746 +
gcc/config/riscv/riscv-vector-builtins.def | 37 +
gcc/config/riscv/riscv-vector-builtins.h | 62 +
gcc/config/riscv/riscv-vector.cc | 1197 +
gcc/config/riscv/riscv-vector.h | 26 +
gcc/config/riscv/riscv.cc | 1001 +-
gcc/config/riscv/riscv.h | 106 +-
gcc/config/riscv/riscv.md | 170 +-
gcc/config/riscv/riscv.opt | 32 +
gcc/config/riscv/riscv_vector.h | 41 +
gcc/config/riscv/t-riscv | 44 +
gcc/config/riscv/vector-iterators.md | 1067 +
gcc/config/riscv/vector.md | 6032 ++
.../g++.target/riscv/rvv/misc_func.C | 2597 +
.../g++.target/riscv/rvv/rvv-intrinsic.exp | 39 +
gcc/testsuite/g++.target/riscv/rvv/set-get.C | 730 +
gcc/testsuite/g++.target/riscv/rvv/vaadd.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vaaddu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vadc.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vadd.C | 10565 +++
gcc/testsuite/g++.target/riscv/rvv/vand.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vasub.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vasubu.C | 5637 ++
.../g++.target/riscv/rvv/vcompress.C | 2550 +
gcc/testsuite/g++.target/riscv/rvv/vcpop.C | 229 +
gcc/testsuite/g++.target/riscv/rvv/vdiv.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vdivu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vfabs.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfadd.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfclass.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vfcvt.C | 6918 ++
gcc/testsuite/g++.target/riscv/rvv/vfdiv.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfirst.C | 229 +
gcc/testsuite/g++.target/riscv/rvv/vfmacc.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmadd.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmax.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmerge.C | 438 +
gcc/testsuite/g++.target/riscv/rvv/vfmin.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmsac.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmsub.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmul.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfmv.C | 726 +
gcc/testsuite/g++.target/riscv/rvv/vfncvt.C | 6662 ++
gcc/testsuite/g++.target/riscv/rvv/vfneg.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfnmacc.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfnmadd.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfnmsac.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfnmsub.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfrdiv.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfrec7.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfredmax.C | 870 +
gcc/testsuite/g++.target/riscv/rvv/vfredmin.C | 870 +
.../g++.target/riscv/rvv/vfredosum.C | 870 +
.../g++.target/riscv/rvv/vfredusum.C | 870 +
gcc/testsuite/g++.target/riscv/rvv/vfrsqrt7.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfrsub.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfsgnj.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfsgnjn.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfsgnjx.C | 2310 +
.../g++.target/riscv/rvv/vfslide1down.C | 1158 +
.../g++.target/riscv/rvv/vfslide1up.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfsqrt.C | 1158 +
gcc/testsuite/g++.target/riscv/rvv/vfsub.C | 2310 +
gcc/testsuite/g++.target/riscv/rvv/vfwadd.C | 2054 +
gcc/testsuite/g++.target/riscv/rvv/vfwcvt.C | 4870 ++
gcc/testsuite/g++.target/riscv/rvv/vfwmacc.C | 1030 +
gcc/testsuite/g++.target/riscv/rvv/vfwmsac.C | 1030 +
gcc/testsuite/g++.target/riscv/rvv/vfwmul.C | 1030 +
gcc/testsuite/g++.target/riscv/rvv/vfwnmacc.C | 1030 +
gcc/testsuite/g++.target/riscv/rvv/vfwnmsac.C | 1030 +
.../g++.target/riscv/rvv/vfwredosum.C | 486 +
.../g++.target/riscv/rvv/vfwredusum.C | 486 +
gcc/testsuite/g++.target/riscv/rvv/vfwsub.C | 2054 +
gcc/testsuite/g++.target/riscv/rvv/vid.C | 2821 +
gcc/testsuite/g++.target/riscv/rvv/viota.C | 2821 +
gcc/testsuite/g++.target/riscv/rvv/vlex_1.C | 6792 ++
gcc/testsuite/g++.target/riscv/rvv/vlexff_1.C | 6792 ++
.../g++.target/riscv/rvv/vloxeix_1.C | 8663 +++
.../g++.target/riscv/rvv/vloxeix_2.C | 7191 ++
.../g++.target/riscv/rvv/vloxeix_3.C | 6120 ++
.../g++.target/riscv/rvv/vloxeix_4.C | 2503 +
gcc/testsuite/g++.target/riscv/rvv/vlsex_1.C | 6792 ++
.../g++.target/riscv/rvv/vluxeix_1.C | 8663 +++
.../g++.target/riscv/rvv/vluxeix_2.C | 7191 ++
.../g++.target/riscv/rvv/vluxeix_3.C | 6120 ++
.../g++.target/riscv/rvv/vluxeix_4.C | 2503 +
gcc/testsuite/g++.target/riscv/rvv/vmacc.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vmadc.C | 2821 +
gcc/testsuite/g++.target/riscv/rvv/vmadd.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vmand.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmandn.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmax.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmaxu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmclr.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmerge.C | 4662 ++
gcc/testsuite/g++.target/riscv/rvv/vmfeq.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmfge.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmfgt.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmfle.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmflt.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmfne.C | 1086 +
gcc/testsuite/g++.target/riscv/rvv/vmin.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vminu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmmv.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmnand.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmnor.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmnot.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmor.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmorn.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmsbc.C | 2821 +
gcc/testsuite/g++.target/riscv/rvv/vmsbf.C | 425 +
gcc/testsuite/g++.target/riscv/rvv/vmseq.C | 5285 ++
gcc/testsuite/g++.target/riscv/rvv/vmset.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmsge.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsgeu.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsgt.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsgtu.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsif.C | 425 +
gcc/testsuite/g++.target/riscv/rvv/vmsle.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsleu.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmslt.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsltu.C | 2645 +
gcc/testsuite/g++.target/riscv/rvv/vmsne.C | 5285 ++
gcc/testsuite/g++.target/riscv/rvv/vmsof.C | 425 +
gcc/testsuite/g++.target/riscv/rvv/vmul.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vmulh.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmulhsu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmulhu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vmv.C | 5222 ++
gcc/testsuite/g++.target/riscv/rvv/vmv1r.C | 125 +
gcc/testsuite/g++.target/riscv/rvv/vmv2r.C | 125 +
gcc/testsuite/g++.target/riscv/rvv/vmv4r.C | 125 +
gcc/testsuite/g++.target/riscv/rvv/vmv8r.C | 125 +
gcc/testsuite/g++.target/riscv/rvv/vmxnor.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vmxor.C | 117 +
gcc/testsuite/g++.target/riscv/rvv/vnclip.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vnclipu.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vncvt.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vneg.C | 2821 +
gcc/testsuite/g++.target/riscv/rvv/vnmsac.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vnmsub.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vnot.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vnsra.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vnsrl.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vor.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vredand.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vredmax.C | 2117 +
gcc/testsuite/g++.target/riscv/rvv/vredmaxu.C | 2117 +
gcc/testsuite/g++.target/riscv/rvv/vredmin.C | 2117 +
gcc/testsuite/g++.target/riscv/rvv/vredminu.C | 2117 +
gcc/testsuite/g++.target/riscv/rvv/vredor.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vredsum.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vredxor.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vrem.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vremu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vrgather.C | 13574 ++++
.../g++.target/riscv/rvv/vrgatherei16.C | 6534 ++
gcc/testsuite/g++.target/riscv/rvv/vrsub.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsadd.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsaddu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsbc.C | 4229 +
gcc/testsuite/g++.target/riscv/rvv/vsetvl.C | 4 +
gcc/testsuite/g++.target/riscv/rvv/vsex.C | 1704 +
gcc/testsuite/g++.target/riscv/rvv/vsext.C | 3589 +
.../g++.target/riscv/rvv/vslide1down.C | 5637 ++
.../g++.target/riscv/rvv/vslide1up.C | 5637 ++
.../g++.target/riscv/rvv/vslidedown.C | 6367 ++
gcc/testsuite/g++.target/riscv/rvv/vslideup.C | 6367 ++
gcc/testsuite/g++.target/riscv/rvv/vsll.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vsmul.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsoxeix.C | 6120 ++
gcc/testsuite/g++.target/riscv/rvv/vsra.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsrl.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vssex.C | 1704 +
gcc/testsuite/g++.target/riscv/rvv/vssra.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vssrl.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vssub.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vssubu.C | 5637 ++
gcc/testsuite/g++.target/riscv/rvv/vsub.C | 10565 +++
gcc/testsuite/g++.target/riscv/rvv/vsuxeix.C | 6120 ++
gcc/testsuite/g++.target/riscv/rvv/vwadd.C | 7685 ++
gcc/testsuite/g++.target/riscv/rvv/vwaddu.C | 7685 ++
gcc/testsuite/g++.target/riscv/rvv/vwcvt.C | 1925 +
gcc/testsuite/g++.target/riscv/rvv/vwcvtu.C | 1925 +
gcc/testsuite/g++.target/riscv/rvv/vwmacc.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwmaccsu.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwmaccu.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwmaccus.C | 1925 +
gcc/testsuite/g++.target/riscv/rvv/vwmul.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwmulsu.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwmulu.C | 3845 +
gcc/testsuite/g++.target/riscv/rvv/vwredsum.C | 1733 +
.../g++.target/riscv/rvv/vwredsumu.C | 1733 +
gcc/testsuite/g++.target/riscv/rvv/vwsub.C | 7685 ++
gcc/testsuite/g++.target/riscv/rvv/vwsubu.C | 7685 ++
gcc/testsuite/g++.target/riscv/rvv/vxor.C | 11269 +++
gcc/testsuite/g++.target/riscv/rvv/vzext.C | 3589 +
.../riscv/rvv/custom/calling_convention_1.c | 46 +
.../riscv/rvv/custom/rvv-custom.exp | 47 +
.../vx-sew64/rvv-e64-on-rv32.h | 78 +
.../vx-sew64/rvv-intrinsic-execute.exp | 48 +
.../vx-sew64/vadd.vx_i_sew64_on_rv32_m1.c | 33 +
.../vx-sew64/vadd.vx_i_sew64_on_rv32_m2.c | 33 +
.../vx-sew64/vadd.vx_i_sew64_on_rv32_m4.c | 33 +
.../vx-sew64/vadd.vx_i_sew64_on_rv32_m8.c | 33 +
.../vx-sew64/vadd.vx_u_sew64_on_rv32_m1.c | 33 +
.../vx-sew64/vadd.vx_u_sew64_on_rv32_m2.c | 33 +
.../vx-sew64/vadd.vx_u_sew64_on_rv32_m4.c | 33 +
.../vx-sew64/vadd.vx_u_sew64_on_rv32_m8.c | 33 +
.../vx-sew64/vand.vx_i_sew64_on_rv32_m1.c | 33 +
.../vx-sew64/vand.vx_i_sew64_on_rv32_m2.c | 33 +
.../vx-sew64/vand.vx_i_sew64_on_rv32_m4.c | 33 +
.../vx-sew64/vand.vx_i_sew64_on_rv32_m8.c | 33 +
.../vx-sew64/vand.vx_u_sew64_on_rv32_m1.c | 33 +
.../vx-sew64/vand.vx_u_sew64_on_rv32_m2.c | 33 +
.../vx-sew64/vand.vx_u_sew64_on_rv32_m4.c | 33 +
.../vx-sew64/vand.vx_u_sew64_on_rv32_m8.c | 33 +
.../vx-sew64/vmax.vx_i_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vmax.vx_i_sew64_on_rv32_m2.c | 32 +
.../vx-sew64/vmax.vx_i_sew64_on_rv32_m4.c | 32 +
.../vx-sew64/vmax.vx_i_sew64_on_rv32_m8.c | 32 +
.../vx-sew64/vmaxu.vx_u_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vmaxu.vx_u_sew64_on_rv32_m2.c | 32 +
.../vx-sew64/vmaxu.vx_u_sew64_on_rv32_m4.c | 32 +
.../vx-sew64/vmaxu.vx_u_sew64_on_rv32_m8.c | 32 +
.../vx-sew64/vmin.vx_i_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vmin.vx_i_sew64_on_rv32_m2.c | 32 +
.../vx-sew64/vmin.vx_i_sew64_on_rv32_m4.c | 32 +
.../vx-sew64/vmin.vx_i_sew64_on_rv32_m8.c | 32 +
.../vx-sew64/vminu.vx_u_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vminu.vx_u_sew64_on_rv32_m2.c | 32 +
.../vx-sew64/vminu.vx_u_sew64_on_rv32_m4.c | 32 +
.../vx-sew64/vminu.vx_u_sew64_on_rv32_m8.c | 32 +
.../vx-sew64/vmv.s.x_i_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vmv.s.x_i_sew64_on_rv32_m2.c | 32 +
.../vx-sew64/vmv.s.x_i_sew64_on_rv32_m4.c | 32 +
.../vx-sew64/vmv.s.x_i_sew64_on_rv32_m8.c | 32 +
.../vx-sew64/vmv.s.x_u_sew64_on_rv32_m1.c | 32 +
.../vx-sew64/vmv.s.x_u_sew64_on_rv32_m2.c | 32 +
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.../vmulhsu.vx_iu_tx_sew64_on_rv32.c | 200 +
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.../vmv.s.x_i_tx_sew64_on_rv32.c | 176 +
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.../vmv.v.x_i_sew64_on_rv32_e64.c | 92 +
.../vmv.v.x_i_tx_sew64_on_rv32_e64.c | 176 +
.../vmv.v.x_u_sew64_on_rv32_e64.c | 92 +
.../vmv.v.x_u_tx_sew64_on_rv32_e64.c | 176 +
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.../vsaddu.vx_u_tx_sew64_on_rv32.c | 200 +
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.../vsbc.vxm_i_tx_sew64_on_rv32.c | 200 +
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.../vsbc.vxm_u_tx_sew64_on_rv32.c | 200 +
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.../vslide1down.vx_i_sew64_on_rv32_e64.c | 104 +
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.../vslide1down.vx_u_tx_sew64_on_rv32_e64.c | 200 +
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.../vslide1up.vx_i_sew64_on_rv32_e64.c | 104 +
.../vslide1up.vx_i_tx_sew64_on_rv32_e64.c | 200 +
.../vslide1up.vx_i_txmx_sew64_on_rv32_e64.c | 392 +
.../vslide1up.vx_u_mask_sew64_on_rv32_e64.c | 104 +
.../vslide1up.vx_u_sew64_on_rv32_e64.c | 104 +
.../vslide1up.vx_u_tx_sew64_on_rv32_e64.c | 200 +
.../vslide1up.vx_u_txmx_sew64_on_rv32_e64.c | 392 +
.../vsmul.vx_i_mask_sew64_on_rv32.c | 104 +
.../vsmul.vx_i_sew64_on_rv32.c | 104 +
.../vsmul.vx_i_tx_sew64_on_rv32.c | 200 +
.../vsmul.vx_i_txmx_sew64_on_rv32.c | 392 +
.../vssub.vx_i_mask_sew64_on_rv32.c | 104 +
.../vssub.vx_i_sew64_on_rv32.c | 104 +
.../vssub.vx_i_tx_sew64_on_rv32.c | 200 +
.../vssub.vx_i_txmx_sew64_on_rv32.c | 392 +
.../vssubu.vx_u_mask_sew64_on_rv32.c | 104 +
.../vssubu.vx_u_sew64_on_rv32.c | 104 +
.../vssubu.vx_u_tx_sew64_on_rv32.c | 200 +
.../vssubu.vx_u_txmx_sew64_on_rv32.c | 392 +
.../vsub.vx_i_mask_sew64_on_rv32.c | 104 +
.../vsub.vx_i_sew64_on_rv32.c | 104 +
.../vsub.vx_i_tx_sew64_on_rv32.c | 200 +
.../vsub.vx_i_txmx_sew64_on_rv32.c | 392 +
.../vsub.vx_u_mask_sew64_on_rv32.c | 104 +
.../vsub.vx_u_sew64_on_rv32.c | 104 +
.../vsub.vx_u_tx_sew64_on_rv32.c | 200 +
.../vsub.vx_u_txmx_sew64_on_rv32.c | 392 +
.../vxor.vx_i_mask_sew64_on_rv32.c | 104 +
.../vxor.vx_i_sew64_on_rv32.c | 104 +
.../vxor.vx_i_tx_sew64_on_rv32.c | 200 +
.../vxor.vx_i_txmx_sew64_on_rv32.c | 392 +
.../vxor.vx_u_mask_sew64_on_rv32.c | 104 +
.../vxor.vx_u_sew64_on_rv32.c | 104 +
.../vxor.vx_u_tx_sew64_on_rv32.c | 200 +
.../vxor.vx_u_txmx_sew64_on_rv32.c | 392 +
.../rvv/intrinsic-rv32/rvv-intrinsic-rv32.exp | 44 +
.../vaadd.vx_i_mask_sew64_on_rv32.c | 40 +
.../vaadd.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vaadd.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vaadd.vx_i_sew64_on_rv32.c | 40 +
.../vaadd.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vaadd.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vaadd.vx_i_tx_sew64_on_rv32.c | 72 +
.../vaadd.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vaadd.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vaadd.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vaadd.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vaadd.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vaaddu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vaaddu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vaaddu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vaaddu.vx_u_sew64_on_rv32.c | 40 +
.../vaaddu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vaaddu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vaaddu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vaaddu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vaaddu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vaaddu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vaaddu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vaaddu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../intrinsic-rv32/vadc.vxm_i_sew64_on_rv32.c | 40 +
.../vadc.vxm_i_sew64_on_rv32_vl31.c | 40 +
.../vadc.vxm_i_sew64_on_rv32_vl32.c | 40 +
.../vadc.vxm_i_tx_sew64_on_rv32.c | 72 +
.../vadc.vxm_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vadc.vxm_i_tx_sew64_on_rv32_vl32.c | 72 +
.../intrinsic-rv32/vadc.vxm_u_sew64_on_rv32.c | 40 +
.../vadc.vxm_u_sew64_on_rv32_vl31.c | 40 +
.../vadc.vxm_u_sew64_on_rv32_vl32.c | 40 +
.../vadc.vxm_u_tx_sew64_on_rv32.c | 72 +
.../vadc.vxm_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vadc.vxm_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vadd.vx_i_mask_sew64_on_rv32.c | 40 +
.../vadd.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vadd.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vadd.vx_i_sew64_on_rv32.c | 40 +
.../vadd.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vadd.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vadd.vx_i_tx_sew64_on_rv32.c | 72 +
.../vadd.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vadd.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vadd.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vadd.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vadd.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vadd.vx_u_mask_sew64_on_rv32.c | 40 +
.../vadd.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vadd.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vadd.vx_u_sew64_on_rv32.c | 40 +
.../vadd.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vadd.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vadd.vx_u_tx_sew64_on_rv32.c | 72 +
.../vadd.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vadd.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vadd.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vadd.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vadd.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vand.vx_i_mask_sew64_on_rv32.c | 40 +
.../vand.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vand.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vand.vx_i_sew64_on_rv32.c | 40 +
.../vand.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vand.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vand.vx_i_tx_sew64_on_rv32.c | 72 +
.../vand.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vand.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vand.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vand.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vand.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vand.vx_u_mask_sew64_on_rv32.c | 40 +
.../vand.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vand.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vand.vx_u_sew64_on_rv32.c | 40 +
.../vand.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vand.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vand.vx_u_tx_sew64_on_rv32.c | 72 +
.../vand.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vand.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vand.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vand.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vand.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vasub.vx_i_mask_sew64_on_rv32.c | 40 +
.../vasub.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vasub.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vasub.vx_i_sew64_on_rv32.c | 40 +
.../vasub.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vasub.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vasub.vx_i_tx_sew64_on_rv32.c | 72 +
.../vasub.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vasub.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vasub.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vasub.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vasub.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vasubu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vasubu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vasubu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vasubu.vx_u_sew64_on_rv32.c | 40 +
.../vasubu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vasubu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vasubu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vasubu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vasubu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vasubu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vasubu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vasubu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vdiv.vx_i_mask_sew64_on_rv32.c | 40 +
.../vdiv.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vdiv.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vdiv.vx_i_sew64_on_rv32.c | 40 +
.../vdiv.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vdiv.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vdiv.vx_i_tx_sew64_on_rv32.c | 72 +
.../vdiv.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vdiv.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vdiv.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vdiv.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vdiv.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vdivu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vdivu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vdivu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vdivu.vx_u_sew64_on_rv32.c | 40 +
.../vdivu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vdivu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vdivu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vdivu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vdivu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vdivu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vdivu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vdivu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmacc.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmacc.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmacc.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmacc.vx_i_sew64_on_rv32.c | 40 +
.../vmacc.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmacc.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmacc.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmacc.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmacc.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmacc.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmacc.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmacc.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmacc.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmacc.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmacc.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmacc.vx_u_sew64_on_rv32.c | 40 +
.../vmacc.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmacc.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmacc.vx_u_tx_sew64_on_rv32.c | 72 +
.../vmacc.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vmacc.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vmacc.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vmacc.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmacc.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../intrinsic-rv32/vmadc.vx_i_sew64_on_rv32.c | 40 +
.../vmadc.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmadc.vx_i_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmadc.vx_u_sew64_on_rv32.c | 40 +
.../vmadc.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmadc.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmadc.vxm_i_sew64_on_rv32.c | 40 +
.../vmadc.vxm_i_sew64_on_rv32_vl31.c | 40 +
.../vmadc.vxm_i_sew64_on_rv32_vl32.c | 40 +
.../vmadc.vxm_u_sew64_on_rv32.c | 40 +
.../vmadc.vxm_u_sew64_on_rv32_vl31.c | 40 +
.../vmadc.vxm_u_sew64_on_rv32_vl32.c | 40 +
.../vmadd.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmadd.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmadd.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmadd.vx_i_sew64_on_rv32.c | 40 +
.../vmadd.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmadd.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmadd.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmadd.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmadd.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmadd.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmadd.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmadd.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmadd.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmadd.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmadd.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmadd.vx_u_sew64_on_rv32.c | 40 +
.../vmadd.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmadd.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmadd.vx_u_tx_sew64_on_rv32.c | 72 +
.../vmadd.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vmadd.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vmadd.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vmadd.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmadd.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmax.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmax.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmax.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmax.vx_i_sew64_on_rv32.c | 40 +
.../vmax.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmax.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmax.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmax.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmax.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmax.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmax.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmax.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmaxu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmaxu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmaxu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmaxu.vx_u_sew64_on_rv32.c | 40 +
.../vmaxu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmaxu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmaxu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vmaxu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vmaxu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vmaxu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vmaxu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmaxu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmerge.vxm_i_sew64_on_rv32.c | 36 +
.../vmerge.vxm_i_sew64_on_rv32_vl31.c | 36 +
.../vmerge.vxm_i_sew64_on_rv32_vl32.c | 36 +
.../vmerge.vxm_i_tx_sew64_on_rv32.c | 64 +
.../vmerge.vxm_i_tx_sew64_on_rv32_vl31.c | 64 +
.../vmerge.vxm_i_tx_sew64_on_rv32_vl32.c | 64 +
.../vmerge.vxm_u_sew64_on_rv32.c | 36 +
.../vmerge.vxm_u_sew64_on_rv32_vl31.c | 36 +
.../vmerge.vxm_u_sew64_on_rv32_vl32.c | 36 +
.../vmerge.vxm_u_tx_sew64_on_rv32.c | 64 +
.../vmerge.vxm_u_tx_sew64_on_rv32_vl31.c | 64 +
.../vmerge.vxm_u_tx_sew64_on_rv32_vl32.c | 64 +
.../vmin.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmin.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmin.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmin.vx_i_sew64_on_rv32.c | 40 +
.../vmin.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmin.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmin.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmin.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmin.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmin.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmin.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmin.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vminu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vminu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vminu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vminu.vx_u_sew64_on_rv32.c | 40 +
.../vminu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vminu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vminu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vminu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vminu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vminu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vminu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vminu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../intrinsic-rv32/vmsbc.vx_i_sew64_on_rv32.c | 40 +
.../vmsbc.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmsbc.vx_i_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsbc.vx_u_sew64_on_rv32.c | 40 +
.../vmsbc.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsbc.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmsbc.vxm_i_sew64_on_rv32.c | 40 +
.../vmsbc.vxm_i_sew64_on_rv32_vl31.c | 40 +
.../vmsbc.vxm_i_sew64_on_rv32_vl32.c | 40 +
.../vmsbc.vxm_u_sew64_on_rv32.c | 40 +
.../vmsbc.vxm_u_sew64_on_rv32_vl31.c | 40 +
.../vmsbc.vxm_u_sew64_on_rv32_vl32.c | 40 +
.../vmseq.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmseq.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmseq.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmseq.vx_i_sew64_on_rv32.c | 40 +
.../vmseq.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmseq.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmseq.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmseq.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmseq.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmseq.vx_u_sew64_on_rv32.c | 40 +
.../vmseq.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmseq.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmsge.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmsge.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsge.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsge.vx_i_sew64_on_rv32.c | 40 +
.../vmsge.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmsge.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmsgeu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmsgeu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsgeu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vmsgeu.vx_u_sew64_on_rv32.c | 40 +
.../vmsgeu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsgeu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmsgt.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmsgt.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsgt.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsgt.vx_i_sew64_on_rv32.c | 40 +
.../vmsgt.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmsgt.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmsgtu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmsgtu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsgtu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vmsgtu.vx_u_sew64_on_rv32.c | 40 +
.../vmsgtu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsgtu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmsle.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmsle.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsle.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsle.vx_i_sew64_on_rv32.c | 40 +
.../vmsle.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmsle.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmsleu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmsleu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsleu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vmsleu.vx_u_sew64_on_rv32.c | 40 +
.../vmsleu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsleu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmslt.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmslt.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmslt.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmslt.vx_i_sew64_on_rv32.c | 40 +
.../vmslt.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmslt.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmsltu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmsltu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsltu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vmsltu.vx_u_sew64_on_rv32.c | 40 +
.../vmsltu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsltu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmsne.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmsne.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsne.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsne.vx_i_sew64_on_rv32.c | 40 +
.../vmsne.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmsne.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmsne.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmsne.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmsne.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmsne.vx_u_sew64_on_rv32.c | 40 +
.../vmsne.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmsne.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmul.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmul.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmul.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmul.vx_i_sew64_on_rv32.c | 40 +
.../vmul.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmul.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmul.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmul.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmul.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmul.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmul.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmul.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmul.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmul.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmul.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmul.vx_u_sew64_on_rv32.c | 40 +
.../vmul.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmul.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmul.vx_u_tx_sew64_on_rv32.c | 72 +
.../vmul.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vmul.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vmul.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vmul.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmul.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmulh.vx_i_mask_sew64_on_rv32.c | 40 +
.../vmulh.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vmulh.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vmulh.vx_i_sew64_on_rv32.c | 40 +
.../vmulh.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vmulh.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vmulh.vx_i_tx_sew64_on_rv32.c | 72 +
.../vmulh.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vmulh.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vmulh.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vmulh.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmulh.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmulhsu.vx_iu_mask_sew64_on_rv32.c | 40 +
.../vmulhsu.vx_iu_mask_sew64_on_rv32_vl31.c | 40 +
.../vmulhsu.vx_iu_mask_sew64_on_rv32_vl32.c | 40 +
.../vmulhsu.vx_iu_sew64_on_rv32.c | 40 +
.../vmulhsu.vx_iu_sew64_on_rv32_vl31.c | 40 +
.../vmulhsu.vx_iu_sew64_on_rv32_vl32.c | 40 +
.../vmulhsu.vx_iu_tx_sew64_on_rv32.c | 72 +
.../vmulhsu.vx_iu_tx_sew64_on_rv32_vl31.c | 72 +
.../vmulhsu.vx_iu_tx_sew64_on_rv32_vl32.c | 72 +
.../vmulhsu.vx_iu_txmx_sew64_on_rv32.c | 136 +
.../vmulhsu.vx_iu_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmulhsu.vx_iu_txmx_sew64_on_rv32_vl32.c | 136 +
.../vmulhu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vmulhu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vmulhu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vmulhu.vx_u_sew64_on_rv32.c | 40 +
.../vmulhu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vmulhu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vmulhu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vmulhu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vmulhu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vmulhu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vmulhu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vmulhu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vnmsac.vx_i_mask_sew64_on_rv32.c | 40 +
.../vnmsac.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vnmsac.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../vnmsac.vx_i_sew64_on_rv32.c | 40 +
.../vnmsac.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vnmsac.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vnmsac.vx_i_tx_sew64_on_rv32.c | 72 +
.../vnmsac.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vnmsac.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vnmsac.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vnmsac.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vnmsac.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vnmsac.vx_u_mask_sew64_on_rv32.c | 40 +
.../vnmsac.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vnmsac.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vnmsac.vx_u_sew64_on_rv32.c | 40 +
.../vnmsac.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vnmsac.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vnmsac.vx_u_tx_sew64_on_rv32.c | 72 +
.../vnmsac.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vnmsac.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vnmsac.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vnmsac.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vnmsac.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vnmsub.vx_i_mask_sew64_on_rv32.c | 40 +
.../vnmsub.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vnmsub.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../vnmsub.vx_i_sew64_on_rv32.c | 40 +
.../vnmsub.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vnmsub.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vnmsub.vx_i_tx_sew64_on_rv32.c | 72 +
.../vnmsub.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vnmsub.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vnmsub.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vnmsub.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vnmsub.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vnmsub.vx_u_mask_sew64_on_rv32.c | 40 +
.../vnmsub.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vnmsub.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vnmsub.vx_u_sew64_on_rv32.c | 40 +
.../vnmsub.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vnmsub.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vnmsub.vx_u_tx_sew64_on_rv32.c | 72 +
.../vnmsub.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vnmsub.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vnmsub.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vnmsub.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vnmsub.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vor.vx_i_mask_sew64_on_rv32.c | 40 +
.../vor.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vor.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vor.vx_i_sew64_on_rv32.c | 40 +
.../vor.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vor.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vor.vx_i_tx_sew64_on_rv32.c | 72 +
.../vor.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vor.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vor.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vor.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vor.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vor.vx_u_mask_sew64_on_rv32.c | 40 +
.../vor.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vor.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vor.vx_u_sew64_on_rv32.c | 40 +
.../vor.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vor.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vor.vx_u_tx_sew64_on_rv32.c | 72 +
.../vor.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vor.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vor.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vor.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vor.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vrem.vx_i_mask_sew64_on_rv32.c | 40 +
.../vrem.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vrem.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vrem.vx_i_sew64_on_rv32.c | 40 +
.../vrem.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vrem.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vrem.vx_i_tx_sew64_on_rv32.c | 72 +
.../vrem.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vrem.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vrem.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vrem.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vrem.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vremu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vremu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vremu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vremu.vx_u_sew64_on_rv32.c | 40 +
.../vremu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vremu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vremu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vremu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vremu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vremu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vremu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vremu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vrsub.vx_i_mask_pseudo_sew64_on_rv32.c | 40 +
...rsub.vx_i_mask_pseudo_sew64_on_rv32_vl31.c | 40 +
...rsub.vx_i_mask_pseudo_sew64_on_rv32_vl32.c | 40 +
.../vrsub.vx_i_pseudo_sew64_on_rv32.c | 40 +
.../vrsub.vx_i_pseudo_sew64_on_rv32_vl31.c | 40 +
.../vrsub.vx_i_pseudo_sew64_on_rv32_vl32.c | 40 +
.../vrsub.vx_i_tx_pseudo_sew64_on_rv32.c | 72 +
.../vrsub.vx_i_tx_pseudo_sew64_on_rv32_vl31.c | 72 +
.../vrsub.vx_i_tx_pseudo_sew64_on_rv32_vl32.c | 72 +
.../vrsub.vx_i_txmx_pseudo_sew64_on_rv32.c | 136 +
...rsub.vx_i_txmx_pseudo_sew64_on_rv32_vl31.c | 136 +
...rsub.vx_i_txmx_pseudo_sew64_on_rv32_vl32.c | 136 +
.../vrsub.vx_u_mask_pseudo_sew64_on_rv32.c | 40 +
...rsub.vx_u_mask_pseudo_sew64_on_rv32_vl31.c | 40 +
...rsub.vx_u_mask_pseudo_sew64_on_rv32_vl32.c | 40 +
.../vrsub.vx_u_pseudo_sew64_on_rv32.c | 40 +
.../vrsub.vx_u_pseudo_sew64_on_rv32_vl31.c | 40 +
.../vrsub.vx_u_pseudo_sew64_on_rv32_vl32.c | 40 +
.../vrsub.vx_u_tx_pseudo_sew64_on_rv32.c | 72 +
.../vrsub.vx_u_tx_pseudo_sew64_on_rv32_vl31.c | 72 +
.../vrsub.vx_u_tx_pseudo_sew64_on_rv32_vl32.c | 72 +
.../vrsub.vx_u_txmx_pseudo_sew64_on_rv32.c | 136 +
...rsub.vx_u_txmx_pseudo_sew64_on_rv32_vl31.c | 136 +
...rsub.vx_u_txmx_pseudo_sew64_on_rv32_vl32.c | 136 +
.../vsadd.vx_i_mask_sew64_on_rv32.c | 40 +
.../vsadd.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vsadd.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vsadd.vx_i_sew64_on_rv32.c | 40 +
.../vsadd.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vsadd.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vsadd.vx_i_tx_sew64_on_rv32.c | 72 +
.../vsadd.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vsadd.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vsadd.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vsadd.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vsadd.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vsaddu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vsaddu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vsaddu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vsaddu.vx_u_sew64_on_rv32.c | 40 +
.../vsaddu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vsaddu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vsaddu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vsaddu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vsaddu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vsaddu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vsaddu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vsaddu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../intrinsic-rv32/vsbc.vxm_i_sew64_on_rv32.c | 40 +
.../vsbc.vxm_i_sew64_on_rv32_vl31.c | 40 +
.../vsbc.vxm_i_sew64_on_rv32_vl32.c | 40 +
.../vsbc.vxm_i_tx_sew64_on_rv32.c | 72 +
.../vsbc.vxm_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vsbc.vxm_i_tx_sew64_on_rv32_vl32.c | 72 +
.../intrinsic-rv32/vsbc.vxm_u_sew64_on_rv32.c | 40 +
.../vsbc.vxm_u_sew64_on_rv32_vl31.c | 40 +
.../vsbc.vxm_u_sew64_on_rv32_vl32.c | 40 +
.../vsbc.vxm_u_tx_sew64_on_rv32.c | 72 +
.../vsbc.vxm_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vsbc.vxm_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vsmul.vx_i_mask_sew64_on_rv32.c | 40 +
.../vsmul.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vsmul.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vsmul.vx_i_sew64_on_rv32.c | 40 +
.../vsmul.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vsmul.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vsmul.vx_i_tx_sew64_on_rv32.c | 72 +
.../vsmul.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vsmul.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vsmul.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vsmul.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vsmul.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vssub.vx_i_mask_sew64_on_rv32.c | 40 +
.../vssub.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vssub.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vssub.vx_i_sew64_on_rv32.c | 40 +
.../vssub.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vssub.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vssub.vx_i_tx_sew64_on_rv32.c | 72 +
.../vssub.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vssub.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vssub.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vssub.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vssub.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vssubu.vx_u_mask_sew64_on_rv32.c | 40 +
.../vssubu.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vssubu.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../vssubu.vx_u_sew64_on_rv32.c | 40 +
.../vssubu.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vssubu.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vssubu.vx_u_tx_sew64_on_rv32.c | 72 +
.../vssubu.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vssubu.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vssubu.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vssubu.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vssubu.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vsub.vx_i_mask_sew64_on_rv32.c | 40 +
.../vsub.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vsub.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vsub.vx_i_sew64_on_rv32.c | 40 +
.../vsub.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vsub.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vsub.vx_i_tx_sew64_on_rv32.c | 72 +
.../vsub.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vsub.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vsub.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vsub.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vsub.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vsub.vx_u_mask_sew64_on_rv32.c | 40 +
.../vsub.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vsub.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vsub.vx_u_sew64_on_rv32.c | 40 +
.../vsub.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vsub.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vsub.vx_u_tx_sew64_on_rv32.c | 72 +
.../vsub.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vsub.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vsub.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vsub.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vsub.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../vxor.vx_i_mask_sew64_on_rv32.c | 40 +
.../vxor.vx_i_mask_sew64_on_rv32_vl31.c | 40 +
.../vxor.vx_i_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vxor.vx_i_sew64_on_rv32.c | 40 +
.../vxor.vx_i_sew64_on_rv32_vl31.c | 40 +
.../vxor.vx_i_sew64_on_rv32_vl32.c | 40 +
.../vxor.vx_i_tx_sew64_on_rv32.c | 72 +
.../vxor.vx_i_tx_sew64_on_rv32_vl31.c | 72 +
.../vxor.vx_i_tx_sew64_on_rv32_vl32.c | 72 +
.../vxor.vx_i_txmx_sew64_on_rv32.c | 136 +
.../vxor.vx_i_txmx_sew64_on_rv32_vl31.c | 136 +
.../vxor.vx_i_txmx_sew64_on_rv32_vl32.c | 136 +
.../vxor.vx_u_mask_sew64_on_rv32.c | 40 +
.../vxor.vx_u_mask_sew64_on_rv32_vl31.c | 40 +
.../vxor.vx_u_mask_sew64_on_rv32_vl32.c | 40 +
.../intrinsic-rv32/vxor.vx_u_sew64_on_rv32.c | 40 +
.../vxor.vx_u_sew64_on_rv32_vl31.c | 40 +
.../vxor.vx_u_sew64_on_rv32_vl32.c | 40 +
.../vxor.vx_u_tx_sew64_on_rv32.c | 72 +
.../vxor.vx_u_tx_sew64_on_rv32_vl31.c | 72 +
.../vxor.vx_u_tx_sew64_on_rv32_vl32.c | 72 +
.../vxor.vx_u_txmx_sew64_on_rv32.c | 136 +
.../vxor.vx_u_txmx_sew64_on_rv32_vl31.c | 136 +
.../vxor.vx_u_txmx_sew64_on_rv32_vl32.c | 136 +
.../riscv/rvv/intrinsic/mask_load_store.c | 77 +
.../riscv/rvv/intrinsic/mask_load_store_31.c | 77 +
.../riscv/rvv/intrinsic/mask_load_store_32.c | 77 +
.../riscv/rvv/intrinsic/misc_func.c | 2921 +
.../riscv/rvv/intrinsic/rvv-intrinsic.exp | 47 +
.../gcc.target/riscv/rvv/intrinsic/set-get.c | 730 +
.../gcc.target/riscv/rvv/intrinsic/vaadd.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vaaddu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vadc.c | 23767 ++++++
.../gcc.target/riscv/rvv/intrinsic/vadd.c | 59408 +++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vand.c | 63631 ++++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vasub.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vasubu.c | 15847 ++++
.../riscv/rvv/intrinsic/vcompress.c | 7161 ++
.../gcc.target/riscv/rvv/intrinsic/vcpop.c | 637 +
.../gcc.target/riscv/rvv/intrinsic/vdiv.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vdivu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vfabs.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfadd.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfclass.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vfcvt.c | 19446 +++++
.../gcc.target/riscv/rvv/intrinsic/vfdiv.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfirst.c | 637 +
.../gcc.target/riscv/rvv/intrinsic/vfmacc.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmadd.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmax.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmerge.c | 1221 +
.../gcc.target/riscv/rvv/intrinsic/vfmin.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmsac.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmsub.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmul.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfmv.c | 2571 +
.../gcc.target/riscv/rvv/intrinsic/vfncvt.c | 18726 +++++
.../gcc.target/riscv/rvv/intrinsic/vfneg.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfnmacc.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfnmadd.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfnmsac.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfnmsub.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfrdiv.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfrec7.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfredmax.c | 2436 +
.../gcc.target/riscv/rvv/intrinsic/vfredmin.c | 2436 +
.../riscv/rvv/intrinsic/vfredosum.c | 2436 +
.../riscv/rvv/intrinsic/vfredusum.c | 2436 +
.../gcc.target/riscv/rvv/intrinsic/vfrsqrt7.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfrsub.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfsgnj.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfsgnjn.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfsgnjx.c | 6486 ++
.../riscv/rvv/intrinsic/vfslide1down.c | 3246 +
.../riscv/rvv/intrinsic/vfslide1up.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfsqrt.c | 3246 +
.../gcc.target/riscv/rvv/intrinsic/vfsub.c | 6486 ++
.../gcc.target/riscv/rvv/intrinsic/vfwadd.c | 5766 ++
.../gcc.target/riscv/rvv/intrinsic/vfwcvt.c | 13686 ++++
.../gcc.target/riscv/rvv/intrinsic/vfwmacc.c | 2886 +
.../gcc.target/riscv/rvv/intrinsic/vfwmsac.c | 2886 +
.../gcc.target/riscv/rvv/intrinsic/vfwmul.c | 2886 +
.../gcc.target/riscv/rvv/intrinsic/vfwnmacc.c | 2886 +
.../gcc.target/riscv/rvv/intrinsic/vfwnmsac.c | 2886 +
.../riscv/rvv/intrinsic/vfwredosum.c | 1356 +
.../riscv/rvv/intrinsic/vfwredusum.c | 1356 +
.../gcc.target/riscv/rvv/intrinsic/vfwsub.c | 5766 ++
.../gcc.target/riscv/rvv/intrinsic/vid.c | 7927 ++
.../gcc.target/riscv/rvv/intrinsic/viota.c | 7927 ++
.../gcc.target/riscv/rvv/intrinsic/vlex_1.c | 17840 +++++
.../gcc.target/riscv/rvv/intrinsic/vlex_2.c | 1251 +
.../gcc.target/riscv/rvv/intrinsic/vlexff_1.c | 17840 +++++
.../gcc.target/riscv/rvv/intrinsic/vlexff_2.c | 1251 +
.../riscv/rvv/intrinsic/vloxeix_1.c | 16220 ++++
.../riscv/rvv/intrinsic/vloxeix_2.c | 18755 +++++
.../riscv/rvv/intrinsic/vloxeix_3.c | 18320 +++++
.../riscv/rvv/intrinsic/vloxeix_4.c | 15486 ++++
.../gcc.target/riscv/rvv/intrinsic/vlsex_1.c | 17840 +++++
.../gcc.target/riscv/rvv/intrinsic/vlsex_2.c | 1251 +
.../riscv/rvv/intrinsic/vluxeix_1.c | 16220 ++++
.../riscv/rvv/intrinsic/vluxeix_2.c | 18755 +++++
.../riscv/rvv/intrinsic/vluxeix_3.c | 18320 +++++
.../riscv/rvv/intrinsic/vluxeix_4.c | 15486 ++++
.../gcc.target/riscv/rvv/intrinsic/vmacc.c | 31687 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vmadc.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmadd.c | 31687 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vmand.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmandn.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmax.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmaxu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmclr.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmerge.c | 24982 ++++++
.../gcc.target/riscv/rvv/intrinsic/vmfeq.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmfge.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmfgt.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmfle.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmflt.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmfne.c | 3031 +
.../gcc.target/riscv/rvv/intrinsic/vmin.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vminu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmmv.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmnand.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmnor.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmnot.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmor.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmorn.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmsbc.c | 7927 ++
.../gcc.target/riscv/rvv/intrinsic/vmsbf.c | 1184 +
.../gcc.target/riscv/rvv/intrinsic/vmseq.c | 29576 +++++++
.../gcc.target/riscv/rvv/intrinsic/vmset.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmsge.c | 7400 ++
.../gcc.target/riscv/rvv/intrinsic/vmsgeu.c | 7400 ++
.../gcc.target/riscv/rvv/intrinsic/vmsgt.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmsgtu.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmsif.c | 1184 +
.../gcc.target/riscv/rvv/intrinsic/vmsle.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmsleu.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmslt.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmsltu.c | 14792 ++++
.../gcc.target/riscv/rvv/intrinsic/vmsne.c | 29576 +++++++
.../gcc.target/riscv/rvv/intrinsic/vmsof.c | 1184 +
.../gcc.target/riscv/rvv/intrinsic/vmul.c | 31687 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vmulh.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmulhsu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmulhu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vmv1r.c | 119 +
.../gcc.target/riscv/rvv/intrinsic/vmv2r.c | 119 +
.../gcc.target/riscv/rvv/intrinsic/vmv4r.c | 119 +
.../gcc.target/riscv/rvv/intrinsic/vmv8r.c | 119 +
.../gcc.target/riscv/rvv/intrinsic/vmxnor.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vmxor.c | 322 +
.../gcc.target/riscv/rvv/intrinsic/vnclip.c | 21697 ++++++
.../gcc.target/riscv/rvv/intrinsic/vnclipu.c | 21697 ++++++
.../gcc.target/riscv/rvv/intrinsic/vncvt.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vneg.c | 7927 ++
.../gcc.target/riscv/rvv/intrinsic/vnmsac.c | 31687 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vnmsub.c | 31687 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vnot.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vnsra.c | 21697 ++++++
.../gcc.target/riscv/rvv/intrinsic/vnsrl.c | 21697 ++++++
.../gcc.target/riscv/rvv/intrinsic/vor.c | 63631 ++++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vredand.c | 11887 +++
.../gcc.target/riscv/rvv/intrinsic/vredmax.c | 5947 ++
.../gcc.target/riscv/rvv/intrinsic/vredmaxu.c | 5947 ++
.../gcc.target/riscv/rvv/intrinsic/vredmin.c | 5947 ++
.../gcc.target/riscv/rvv/intrinsic/vredminu.c | 5947 ++
.../gcc.target/riscv/rvv/intrinsic/vredor.c | 11887 +++
.../gcc.target/riscv/rvv/intrinsic/vredsum.c | 11887 +++
.../gcc.target/riscv/rvv/intrinsic/vredxor.c | 11887 +++
.../gcc.target/riscv/rvv/intrinsic/vrem.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vremu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vrgather.c | 38166 +++++++++
.../riscv/rvv/intrinsic/vrgatherei16.c | 18366 +++++
.../gcc.target/riscv/rvv/intrinsic/vrsub.c | 47791 ++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vsadd.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vsaddu.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vsbc.c | 11887 +++
.../gcc.target/riscv/rvv/intrinsic/vsetvl.c | 733 +
.../gcc.target/riscv/rvv/intrinsic/vsex.c | 4776 ++
.../gcc.target/riscv/rvv/intrinsic/vsext.c | 10087 +++
.../riscv/rvv/intrinsic/vslide1down.c | 15847 ++++
.../riscv/rvv/intrinsic/vslide1up.c | 15847 ++++
.../riscv/rvv/intrinsic/vslidedown.c | 48176 ++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vslideup.c | 48176 ++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vsll.c | 63631 ++++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vsmul.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vsoxeix.c | 17196 +++++
.../gcc.target/riscv/rvv/intrinsic/vsra.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vsrl.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vssex.c | 4776 ++
.../gcc.target/riscv/rvv/intrinsic/vssra.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vssrl.c | 31819 ++++++++
.../gcc.target/riscv/rvv/intrinsic/vssub.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vssubu.c | 15847 ++++
.../gcc.target/riscv/rvv/intrinsic/vsub.c | 59408 +++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vsuxeix.c | 17196 +++++
.../gcc.target/riscv/rvv/intrinsic/vwadd.c | 21607 ++++++
.../gcc.target/riscv/rvv/intrinsic/vwaddu.c | 21607 ++++++
.../gcc.target/riscv/rvv/intrinsic/vwcvt.c | 5407 ++
.../gcc.target/riscv/rvv/intrinsic/vwcvtu.c | 5407 ++
.../gcc.target/riscv/rvv/intrinsic/vwmacc.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwmaccsu.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwmaccu.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwmaccus.c | 5407 ++
.../gcc.target/riscv/rvv/intrinsic/vwmul.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwmulsu.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwmulu.c | 10807 +++
.../gcc.target/riscv/rvv/intrinsic/vwredsum.c | 4867 ++
.../riscv/rvv/intrinsic/vwredsumu.c | 4867 ++
.../gcc.target/riscv/rvv/intrinsic/vwsub.c | 21607 ++++++
.../gcc.target/riscv/rvv/intrinsic/vwsubu.c | 21607 ++++++
.../gcc.target/riscv/rvv/intrinsic/vxor.c | 63631 ++++++++++++++++
.../gcc.target/riscv/rvv/intrinsic/vzext.c | 10087 +++
.../gcc.target/riscv/rvv/stack/rvv-stack.exp | 47 +
.../rvv/stack/stack-check-alloca-scalar.c | 53 +
.../rvv/stack/stack-check-alloca-vector.c | 45 +
.../stack/stack-check-save-restore-scalar.c | 48 +
.../stack/stack-check-save-restore-vector.c | 62 +
.../riscv/rvv/stack/stack-check-scalar.c | 205 +
.../rvv/stack/stack-check-vararg-scalar.c | 33 +
.../riscv/rvv/stack/stack-check-vector_1.c | 277 +
.../riscv/rvv/stack/stack-check-vector_2.c | 141 +
1409 files changed, 3197907 insertions(+), 199 deletions(-)
create mode 100644 gcc/config/riscv/md-parser
create mode 100644 gcc/config/riscv/riscv-insert-vsetvl.cc
create mode 100644 gcc/config/riscv/riscv-vector-builtins-functions.cc
create mode 100644 gcc/config/riscv/riscv-vector-builtins-functions.def
create mode 100644 gcc/config/riscv/riscv-vector-builtins-functions.h
create mode 100644 gcc/config/riscv/riscv-vector-builtins-iterators.def
create mode 100644 gcc/config/riscv/riscv-vector-builtins.cc
create mode 100644 gcc/config/riscv/riscv-vector-builtins.def
create mode 100644 gcc/config/riscv/riscv-vector-builtins.h
create mode 100644 gcc/config/riscv/riscv-vector.cc
create mode 100644 gcc/config/riscv/riscv-vector.h
create mode 100644 gcc/config/riscv/riscv_vector.h
create mode 100644 gcc/config/riscv/vector-iterators.md
create mode 100644 gcc/config/riscv/vector.md
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/misc_func.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/rvv-intrinsic.exp
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/set-get.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vaadd.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vaaddu.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vadc.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vand.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vasub.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vcompress.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vdiv.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfabs.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfdiv.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfirst.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfmacc.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfmax.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfrec7.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfredmax.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfslide1down.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vfwsub.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vmfne.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vmsbc.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vmsbf.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vmxnor.C
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create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vredmax.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vredmaxu.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vredmin.C
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--
2.36.1
next reply other threads:[~2022-05-31 8:50 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-31 8:49 juzhe.zhong [this message]
2022-05-31 8:49 ` [PATCH 01/21] Add RVV modes and support scalable vector juzhe.zhong
2022-05-31 8:49 ` [PATCH 02/21] Add RVV intrinsic framework juzhe.zhong
2022-05-31 8:49 ` [PATCH 03/21] Add RVV datatypes juzhe.zhong
2022-05-31 8:49 ` [PATCH 04/21] Add RVV intrinsic enable #pragma riscv intrinsic "vector" and introduce RVV header "riscv_vector.h" juzhe.zhong
2022-05-31 8:49 ` [PATCH 05/21] Add RVV configuration intrinsic juzhe.zhong
2022-05-31 8:49 ` [PATCH 06/21] Add insert-vsetvl pass juzhe.zhong
2022-05-31 8:49 ` [PATCH 07/21] Add register spilling support juzhe.zhong
2022-05-31 8:49 ` [PATCH 08/21] Add poly manipulation juzhe.zhong
2022-05-31 8:50 ` [PATCH 09/21] Add misc function intrinsic support juzhe.zhong
2022-05-31 8:50 ` [PATCH 11/21] Add calling function support juzhe.zhong
2022-05-31 8:50 ` [PATCH 12/21] Add set get intrinsic support juzhe.zhong
2022-05-31 8:50 ` [PATCH 13/21] Adjust scalable frame and full testcases juzhe.zhong
2022-05-31 8:50 ` [PATCH 15/21] Add integer intrinsics juzhe.zhong
2022-05-31 8:50 ` [PATCH 18/21] Add rest intrinsic support juzhe.zhong
2022-05-31 16:51 ` [PATCH 00/21] *** Add RVV (RISC-V 'V' Extension) support *** Palmer Dabbelt
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