From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id C20B63857426 for ; Tue, 31 May 2022 08:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C20B63857426 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1653987028trpkf1jx Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 May 2022 16:50:27 +0800 (CST) X-QQ-SSF: 01400000002000B0F000000A0000000 X-QQ-FEAT: SIq+DGERJtxYukrb5BUeTPSO9/mb/l0Bh1yj2Nh2l/HM1kiyfB6xy91BK7xmw g8eFriwdTKz9YekGvV9J2m9ki5DGsZA+gxDWXSLMCiabvl3fpDytAPZUeBOiPuC459orAyG QCYmeKBlvOT0Tli4Ea++gwEOTaGNpNW7MRc1m7IwVomP/bpeOK1UXfy91rfxwFobpctrqip 6i9Y3Gqz0X6b7pxwTycO6BHZUUHN/Z4J32ZPEs8kpv09RvLvf93VT+EvblAH3C4rutw7wmf xhg5wk/EAG+3dzFIKEYVykcz4BDXSjMdmbPxjyLFAEDjSvQXckxOCgKDIuCWNvdGjXEeR2/ /gc2r5jnjpJO7GxKX4L9JOcvK6wirJ3Ag98RE9aJKw0b0ZlRxw= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai Subject: [PATCH 04/21] Add RVV intrinsic enable #pragma riscv intrinsic "vector" and introduce RVV header "riscv_vector.h" Date: Tue, 31 May 2022 16:49:55 +0800 Message-Id: <20220531085012.269719-5-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220531085012.269719-1-juzhe.zhong@rivai.ai> References: <20220531085012.269719-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign9 X-QQ-Bgrelay: 1 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 May 2022 08:50:43 -0000 From: zhongjuzhe gcc/ChangeLog: * config.gcc: New header. * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): New function. (riscv_check_builtin_call): New function. (riscv_register_pragmas): New function. * config/riscv/riscv-protos.h (riscv_register_pragmas): New function. * config/riscv/riscv.h (REGISTER_TARGET_PRAGMAS): New targethook. * config/riscv/riscv_vector.h: New file. --- gcc/config.gcc | 1 + gcc/config/riscv/riscv-c.cc | 65 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.h | 2 + gcc/config/riscv/riscv_vector.h | 41 +++++++++++++++++++++ 5 files changed, 110 insertions(+) create mode 100644 gcc/config/riscv/riscv_vector.h diff --git a/gcc/config.gcc b/gcc/config.gcc index bdda82ae576..042a7a17737 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -517,6 +517,7 @@ pru-*-*) ;; riscv*) cpu_type=riscv + extra_headers="riscv_vector.h" extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-vector.o riscv-vector-builtins-functions.o riscv-vector-builtins.o" d_target_objs="riscv-d.o" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-builtins.cc \$(srcdir)/config/riscv/riscv-vector-builtins.cc" diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index eb7ef09297e..5839e849092 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -25,9 +25,17 @@ along with GCC; see the file COPYING3. If not see #include "system.h" #include "coretypes.h" #include "tm.h" +#include "input.h" +#include "memmodel.h" +#include "tm_p.h" +#include "flags.h" #include "c-family/c-common.h" #include "cpplib.h" +#include "c-family/c-pragma.h" +#include "langhooks.h" +#include "target.h" #include "riscv-subset.h" +#include "riscv-vector-builtins.h" #define builtin_define(TXT) cpp_define (pfile, TXT) @@ -155,3 +163,60 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define_with_int_value (buf, version_value); } } + +/* Implement "#pragma riscv intrinsic". */ +static void +riscv_pragma_intrinsic (cpp_reader *) +{ + tree x; + + if (pragma_lex (&x) != CPP_STRING) + { + error ("%<#pragma riscv intrinsic%> requires a string parameter"); + return; + } + + const char *name = TREE_STRING_POINTER (x); + + if (strcmp (name, "vector") == 0) + { + if (!TARGET_VECTOR) + error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension enabled", name); + + riscv_vector::handle_pragma_vector (); + } + else + error ("unknown %<#pragma riscv intrinsic%> option %qs", name); +} + +/* Implement TARGET_CHECK_BUILTIN_CALL. */ + +static bool +riscv_check_builtin_call (location_t loc, vec arg_loc, + tree fndecl, tree orig_fndecl, + unsigned int nargs, tree *args) +{ + unsigned int code = DECL_MD_FUNCTION_CODE (fndecl); + unsigned int subcode = code >> RISCV_BUILTIN_SHIFT; + + switch (code & RISCV_BUILTIN_CLASS) + { + case RISCV_BUILTIN_GENERAL: + return true; + + case RISCV_BUILTIN_VECTOR: + return riscv_vector::check_builtin_call (loc, arg_loc, subcode, + orig_fndecl, nargs, args); + } + + gcc_unreachable (); +} + +/* Implement REGISTER_TARGET_PRAGMAS. */ + +void +riscv_register_pragmas (void) +{ + targetm.check_builtin_call = riscv_check_builtin_call; + c_register_pragma ("riscv", "intrinsic", riscv_pragma_intrinsic); +} \ No newline at end of file diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 1cb3586d1f1..4a4ac645f55 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -116,6 +116,7 @@ extern bool rvv_legitimate_poly_int_p (rtx); extern unsigned int rvv_offset_temporaries (bool, poly_int64); extern enum vlmul_field_enum riscv_classify_vlmul_field (machine_mode); extern int rvv_regsize (machine_mode); +extern void riscv_register_pragmas (void); /* We classify builtin types into two classes: 1. General builtin class which is using the diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 8f56a5a4746..cb4cfc0f73e 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1067,4 +1067,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define TARGET_SUPPORTS_WIDE_INT 1 +#define REGISTER_TARGET_PRAGMAS() riscv_register_pragmas () + #endif /* ! GCC_RISCV_H */ diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h new file mode 100644 index 00000000000..ef1820a07cb --- /dev/null +++ b/gcc/config/riscv/riscv_vector.h @@ -0,0 +1,41 @@ +/* Header of intrinsics for RISC-V 'V' Extension for GNU compiler. + Copyright (C) 2021-2021 Free Software Foundation, Inc. + Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai). + Based on MIPS target for GNU compiler. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef __RISCV_VECTOR_H +#define __RISCV_VECTOR_H + +#include +#include + +typedef float float32_t; +typedef double float64_t; + +typedef float __float32_t; +typedef double __float64_t; + +/* NOTE: This implementation of riscv_vector.h is intentionally short. It does + not define the RVV types and intrinsic functions directly in C and C++ + code, but instead uses the following pragma to tell GCC to insert the + necessary type and function definitions itself. The net effect is the + same, and the file is a complete implementation of riscv_vector.h. */ +#pragma riscv intrinsic "vector" + +#endif // __RISCV_VECTOR_H \ No newline at end of file -- 2.36.1