From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
zhongjuzhe <juzhe.zhong@rivai.ai>
Subject: [PATCH v2 0/1] RISC-V: Add RVV (RISC-V 'V' Extension) support
Date: Tue, 31 May 2022 18:33:55 +0800 [thread overview]
Message-ID: <20220531103356.332482-1-juzhe.zhong@rivai.ai> (raw)
From: zhongjuzhe <juzhe.zhong@rivai.ai>
This patch adds implementation which missed in the V1 patch.
*** BLURB HERE ***
zhongjuzhe (1):
Add unit-stride load store intrinsics
.../riscv/riscv-vector-builtins-functions.cc | 80 +++++++++++++++++++
.../riscv/riscv-vector-builtins-functions.def | 7 ++
.../riscv/riscv-vector-builtins-functions.h | 42 ++++++++++
gcc/config/riscv/riscv-vector-builtins.cc | 14 ++++
4 files changed, 143 insertions(+)
--
2.36.1
next reply other threads:[~2022-05-31 10:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-31 10:33 juzhe.zhong [this message]
2022-05-31 10:33 ` [PATCH v2 1/1] Add unit-stride load store intrinsics juzhe.zhong
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