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* [PATCH 00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support
@ 2022-06-01  2:28 juzhe.zhong
  2022-06-01  2:28 ` [PATCH v4 02/34] RISC-V: Add vlex_2.c juzhe.zhong
                   ` (20 more replies)
  0 siblings, 21 replies; 23+ messages in thread
From: juzhe.zhong @ 2022-06-01  2:28 UTC (permalink / raw)
  To: gcc-patches; +Cc: zhongjuzhe

From: zhongjuzhe <juzhe.zhong@rivai.ai>

This patche add the testcases that are missed in v1.

*** BLURB HERE ***

zhongjuzhe (34):
  RISC-V: Add vlex_1.c
  RISC-V: Add vlex_2.c
  RISC-V: Add vlex_1.C
  RISC-V: Add mask load store testcases
  RISC-V: Add vlexff_1.c
  RISC-V: Add vlexff_2.c
  RISC-V: Add vloxeix_1.c
  RISC-V: Add vloxeix_2.c
  RISC-V: Add vloxeix_3.c
  RISC-V: Add vloxeix_4.c
  RISC-V: Add vlsex_1.c
  RISC-V: Add vlsex_2.c
  RISC-V: Add vluxeix_1.c
  RISC-V: Add vluxeix_2.c
  RISC-V: Add vluxeix_3.c
  RISC-V: Add vluxeix_4.c
  RISC-V: Add vsex.c
  RISC-V: Add vsoxeix.c
  RISC-V: Add vssex.c
  RISC-V: Add vsuxeix.c
  RISC-V: Add vlexff_1.C
  RISC-V: Add vloxeix_1.C
  RISC-V: Add vloxeix_2.C
  RISC-V: Add vloxeix_3.C
  RISC-V: Add vloxeix_4.C
  RISC-V: Add vlsex_1.C
  RISC-V: Add vluxeix_1.C
  RISC-V: Add vluxeix_2.C
  RISC-V: Add vluxeix_3.C
  RISC-V: Add vluxeix_4.C
  RISC-V: Add vsex.C
  RISC-V: Add vsoxeix.C
  RISC-V: Add vssex.C
  RISC-V: Add vsuxeix.C

 gcc/testsuite/g++.target/riscv/rvv/vlex_1.C   |  6792 ++++++
 gcc/testsuite/g++.target/riscv/rvv/vlexff_1.C |  6792 ++++++
 .../g++.target/riscv/rvv/vloxeix_1.C          |  8663 +++++++
 .../g++.target/riscv/rvv/vloxeix_2.C          |  7191 ++++++
 .../g++.target/riscv/rvv/vloxeix_3.C          |  6120 +++++
 .../g++.target/riscv/rvv/vloxeix_4.C          |  2503 +++
 gcc/testsuite/g++.target/riscv/rvv/vlsex_1.C  |  6792 ++++++
 .../g++.target/riscv/rvv/vluxeix_1.C          |  8663 +++++++
 .../g++.target/riscv/rvv/vluxeix_2.C          |  7191 ++++++
 .../g++.target/riscv/rvv/vluxeix_3.C          |  6120 +++++
 .../g++.target/riscv/rvv/vluxeix_4.C          |  2503 +++
 gcc/testsuite/g++.target/riscv/rvv/vsex.C     |  1704 ++
 gcc/testsuite/g++.target/riscv/rvv/vsoxeix.C  |  6120 +++++
 gcc/testsuite/g++.target/riscv/rvv/vssex.C    |  1704 ++
 gcc/testsuite/g++.target/riscv/rvv/vsuxeix.C  |  6120 +++++
 .../riscv/rvv/intrinsic/mask_load_store.c     |    77 +
 .../riscv/rvv/intrinsic/mask_load_store_31.c  |    77 +
 .../riscv/rvv/intrinsic/mask_load_store_32.c  |    77 +
 .../gcc.target/riscv/rvv/intrinsic/vlex_1.c   | 17840 +++++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vlex_2.c   |  1251 ++
 .../gcc.target/riscv/rvv/intrinsic/vlexff_1.c | 17840 +++++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vlexff_2.c |  1251 ++
 .../riscv/rvv/intrinsic/vloxeix_1.c           | 16220 +++++++++++++
 .../riscv/rvv/intrinsic/vloxeix_2.c           | 18755 ++++++++++++++++
 .../riscv/rvv/intrinsic/vloxeix_3.c           | 18320 +++++++++++++++
 .../riscv/rvv/intrinsic/vloxeix_4.c           | 15486 +++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vlsex_1.c  | 17840 +++++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vlsex_2.c  |  1251 ++
 .../riscv/rvv/intrinsic/vluxeix_1.c           | 16220 +++++++++++++
 .../riscv/rvv/intrinsic/vluxeix_2.c           | 18755 ++++++++++++++++
 .../riscv/rvv/intrinsic/vluxeix_3.c           | 18320 +++++++++++++++
 .../riscv/rvv/intrinsic/vluxeix_4.c           | 15486 +++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vsex.c     |  4776 ++++
 .../gcc.target/riscv/rvv/intrinsic/vsoxeix.c  | 17196 ++++++++++++++
 .../gcc.target/riscv/rvv/intrinsic/vssex.c    |  4776 ++++
 .../gcc.target/riscv/rvv/intrinsic/vsuxeix.c  | 17196 ++++++++++++++
 36 files changed, 323988 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlex_1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlexff_1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vloxeix_4.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vlsex_1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vluxeix_4.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsex.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsoxeix.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vssex.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/vsuxeix.C
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlex_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlex_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlexff_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlexff_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vloxeix_4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vlsex_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vluxeix_4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsex.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsoxeix.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vssex.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/vsuxeix.c

-- 
2.36.1




^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v4 02/34] RISC-V: Add vlex_2.c
@ 2023-01-05 16:26 Joern Rennecke
  0 siblings, 0 replies; 23+ messages in thread
From: Joern Rennecke @ 2023-01-05 16:26 UTC (permalink / raw)
  To: GCC Patches

On Wed, Jun 1, 2022 at 02:28:45 GMT 2022, zhongjuzhe
<juzhe.zhong@rivai.ai> wrote:
> gcc/testsuite/ChangeLog:
>
>        * gcc.target/riscv/rvv/intrinsic/vlex_2.c: New test.

These intrinsic test cases look like they have been machine generated.  And if
they aren't, they probably should (have) be(en).  I've been working on
stabilizing
a tree with the rvv patches merged, and found a number of tests had diverged
in intrinsic function naming, arguments taken, and/or return type.
Fixing this all
with global replaces in dozens of files is quite messy.  It would be
preferable if
such issues could be fixed by adjusting a generator file, and just re-generating
the generated files.  That's one of the reasons why the GPL makes a point of
asking to include source code.  Even if that is not strictly required
for the testsuite
for license reasons, it makes good sense to do that for maintenance reasons.
The generator file should then also add a note where in the source
tree to find the
generator file, and, where appropriate, notes which part(s) of the
generator file
is/are responsible for generating the test case.

^ permalink raw reply	[flat|nested] 23+ messages in thread

end of thread, other threads:[~2023-01-05 16:27 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-01  2:28 [PATCH 00/34] RISC-V: Add RVV (RISC-V 'V' Extension) support juzhe.zhong
2022-06-01  2:28 ` [PATCH v4 02/34] RISC-V: Add vlex_2.c juzhe.zhong
2022-06-01  2:28 ` [PATCH v4 03/34] RISC-V: Add vlex_1.C juzhe.zhong
2022-06-01  2:28 ` [PATCH v4 04/34] RISC-V: Add mask load store testcases juzhe.zhong
2022-06-01  2:28 ` [PATCH v4 06/34] RISC-V: Add vlexff_2.c juzhe.zhong
2022-06-01  2:28 ` [PATCH v4 12/34] RISC-V: Add vlsex_2.c juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 17/34] RISC-V: Add vsex.c juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 19/34] RISC-V: Add vssex.c juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 21/34] RISC-V: Add vlexff_1.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 22/34] RISC-V: Add vloxeix_1.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 23/34] RISC-V: Add vloxeix_2.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 24/34] RISC-V: Add vloxeix_3.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 25/34] RISC-V: Add vloxeix_4.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 26/34] RISC-V: Add vlsex_1.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 27/34] RISC-V: Add vluxeix_1.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 28/34] RISC-V: Add vluxeix_2.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 29/34] RISC-V: Add vluxeix_3.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 30/34] RISC-V: Add vluxeix_4.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 31/34] RISC-V: Add vsex.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 32/34] RISC-V: Add vsoxeix.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 33/34] RISC-V: Add vssex.C juzhe.zhong
2022-06-01  2:29 ` [PATCH v4 34/34] RISC-V: Add vsuxeix.C juzhe.zhong
2023-01-05 16:26 [PATCH v4 02/34] RISC-V: Add vlex_2.c Joern Rennecke

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