From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpproxy21.qq.com (smtpbg704.qq.com [203.205.195.105]) by sourceware.org (Postfix) with ESMTPS id C09543857B83 for ; Wed, 1 Jun 2022 02:29:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C09543857B83 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1654050572t7xnskqc Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Jun 2022 10:29:32 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: ufm+TBkikDN5vswKb8XVUyMUIv0WIvdvdUFsBl2uUh30LWvHaxfPQEU2C05RF XSnfevhDYPG7G/26atVOBXNkAg4StAeTMaDcJGWjEEHWRVOBVyxY5I0b2qOOz5uIEgm5P/+ TAm3Bp8Wu14w5LrLrXjkaEwa+NPWthnM0SYNNdBJWY8xjrawL6/LxtBtT203lIREE7pMyTd 1S2oYefs6lRZGc6OBuD/4Ih2UtMNhu0meH7Mb/6pRzaxu5YIymKiTt0b/EiS/KEOfL/ZNGF +OZEqyWkAAgw7pEm75D0KITeCuhL5QRyR5L4wpmOOu+e/G3xyWLUwmTOFEAm4Ne/jOHGOv3 uxlDv9H8USvhirWxdI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: zhongjuzhe Subject: [PATCH v4 04/34] RISC-V: Add mask load store testcases Date: Wed, 1 Jun 2022 10:28:47 +0800 Message-Id: <20220601022917.270325-5-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220601022917.270325-1-juzhe.zhong@rivai.ai> References: <20220601022917.270325-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybgforeign:qybgforeign8 X-QQ-Bgrelay: 1 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jun 2022 02:29:42 -0000 From: zhongjuzhe =0D gcc/testsuite/ChangeLog:=0D =0D * gcc.target/riscv/rvv/intrinsic/mask_load_store.c: New test.=0D * gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c: New test.=0D * gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c: New test.=0D =0D ---=0D .../riscv/rvv/intrinsic/mask_load_store.c | 77 +++++++++++++++++++=0D .../riscv/rvv/intrinsic/mask_load_store_31.c | 77 +++++++++++++++++++=0D .../riscv/rvv/intrinsic/mask_load_store_32.c | 77 +++++++++++++++++++=0D 3 files changed, 231 insertions(+)=0D create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_= store.c=0D create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_= store_31.c=0D create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_= store_32.c=0D =0D diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store.c= b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store.c=0D new file mode 100644=0D index 00000000000..01117233024=0D --- /dev/null=0D +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store.c=0D @@ -0,0 +1,77 @@=0D +=0D +/* { dg-do compile } */=0D +/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=3Drv*v= *" } } */=0D +=0D +#include =0D +#include =0D +=0D +=0D +vbool1_t test_vlm_v_b1_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b1(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu\s+vlm\.v\s+(?:v[08]|v16|v= 24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b1 )= ?} 1 } } */=0D +=0D +void test_vsm_v_b1_vl(uint8_t *base, vbool1_t value, size_t vl) {=0D + vsm_v_b1(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu\s+vsm\.v\s+(?:v[08]|v16|v= 24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b1 )= ?} 1 } } */=0D +=0D +vbool2_t test_vlm_v_b2_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b2(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu\s+vlm\.v\s+(?:v[048]|v1[2= 6]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vl= m_v_b2 )?} 1 } } */=0D +=0D +void test_vsm_v_b2_vl(uint8_t *base, vbool2_t value, size_t vl) {=0D + vsm_v_b2(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu\s+vsm\.v\s+(?:v[048]|v1[2= 6]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vs= m_v_b2 )?} 1 } } */=0D +=0D +vbool4_t test_vlm_v_b4_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b4(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu\s+vlm\.v\s+(?:v[02468]|v[= 1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vlm_v_b4 )?} 1 } } */=0D +=0D +void test_vsm_v_b4_vl(uint8_t *base, vbool4_t value, size_t vl) {=0D + vsm_v_b4(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu\s+vsm\.v\s+(?:v[02468]|v[= 1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vsm_v_b4 )?} 1 } } */=0D +=0D +vbool8_t test_vlm_v_b8_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b8(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-= 2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vlm_v_b8 )?} 1 } } */=0D +=0D +void test_vsm_v_b8_vl(uint8_t *base, vbool8_t value, size_t vl) {=0D + vsm_v_b8(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-= 2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vsm_v_b8 )?} 1 } } */=0D +=0D +vbool16_t test_vlm_v_b16_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b16(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b16 )?} 1 } } */=0D +=0D +void test_vsm_v_b16_vl(uint8_t *base, vbool16_t value, size_t vl) {=0D + vsm_v_b16(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b16 )?} 1 } } */=0D +=0D +vbool32_t test_vlm_v_b32_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b32(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b32 )?} 1 } } */=0D +=0D +void test_vsm_v_b32_vl(uint8_t *base, vbool32_t value, size_t vl) {=0D + vsm_v_b32(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b32 )?} 1 } } */=0D +=0D +vbool64_t test_vlm_v_b64_vl(const uint8_t *base, size_t vl) {=0D + return vlm_v_b64(base, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b64 )?} 1 } } */=0D +=0D +void test_vsm_v_b64_vl(uint8_t *base, vbool64_t value, size_t vl) {=0D + vsm_v_b64(base, value, vl);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b64 )?} 1 } } */=0D diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_3= 1.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c=0D new file mode 100644=0D index 00000000000..67f108c577d=0D --- /dev/null=0D +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_31.c=0D @@ -0,0 +1,77 @@=0D +=0D +/* { dg-do compile } */=0D +/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=3Drv*v= *" } } */=0D +=0D +#include =0D +#include =0D +=0D +=0D +vbool1_t test_vlm_v_b1_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b1(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s= *ta,\s*mu\s+vlm\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10= |s11|a[0-7])\)\n(?: test_vlm_v_b1 )?} 1 } } */=0D +=0D +void test_vsm_v_b1_31(uint8_t *base, vbool1_t value, size_t vl) {=0D + vsm_v_b1(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s= *ta,\s*mu\s+vsm\.v\s+(?:v[08]|v16|v24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10= |s11|a[0-7])\)\n(?: test_vsm_v_b1 )?} 1 } } */=0D +=0D +vbool2_t test_vlm_v_b2_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b2(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s= *ta,\s*mu\s+vlm\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[= 0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b2 )?} 1 } } */=0D +=0D +void test_vsm_v_b2_31(uint8_t *base, vbool2_t value, size_t vl) {=0D + vsm_v_b2(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s= *ta,\s*mu\s+vsm\.v\s+(?:v[048]|v1[26]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[= 0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b2 )?} 1 } } */=0D +=0D +vbool4_t test_vlm_v_b4_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b4(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s= *ta,\s*mu\s+vlm\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b4 )?} 1 } } */=0D +=0D +void test_vsm_v_b4_31(uint8_t *base, vbool4_t value, size_t vl) {=0D + vsm_v_b4(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s= *ta,\s*mu\s+vsm\.v\s+(?:v[02468]|v[1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b4 )?} 1 } } */=0D +=0D +vbool8_t test_vlm_v_b8_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b8(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s= *ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b8 )?} 1 } } */=0D +=0D +void test_vsm_v_b8_31(uint8_t *base, vbool8_t value, size_t vl) {=0D + vsm_v_b8(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s= *ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b8 )?} 1 } } */=0D +=0D +vbool16_t test_vlm_v_b16_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b16(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\= s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b16 )?} 1 } } */=0D +=0D +void test_vsm_v_b16_31(uint8_t *base, vbool16_t value, size_t vl) {=0D + vsm_v_b16(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\= s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b16 )?} 1 } } */=0D +=0D +vbool32_t test_vlm_v_b32_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b32(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\= s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b32 )?} 1 } } */=0D +=0D +void test_vsm_v_b32_31(uint8_t *base, vbool32_t value, size_t vl) {=0D + vsm_v_b32(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\= s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b32 )?} 1 } } */=0D +=0D +vbool64_t test_vlm_v_b64_31(const uint8_t *base, size_t vl) {=0D + return vlm_v_b64(base, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\= s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b64 )?} 1 } } */=0D +=0D +void test_vsm_v_b64_31(uint8_t *base, vbool64_t value, size_t vl) {=0D + vsm_v_b64(base, value, 31);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\= s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0= -6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b64 )?} 1 } } */=0D diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_3= 2.c b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c=0D new file mode 100644=0D index 00000000000..fedd0ade60e=0D --- /dev/null=0D +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrinsic/mask_load_store_32.c=0D @@ -0,0 +1,77 @@=0D +=0D +/* { dg-do compile } */=0D +/* { dg-skip-if "test vector intrinsic" { *-*-* } { "*" } { "-march=3Drv*v= *" } } */=0D +=0D +#include =0D +#include =0D +=0D +=0D +vbool1_t test_vlm_v_b1_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b1(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu\s+vlm\.v\s+(?:v[08]|v16|v= 24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vlm_v_b1 )= ?} 1 } } */=0D +=0D +void test_vsm_v_b1_32(uint8_t *base, vbool1_t value, size_t vl) {=0D + vsm_v_b1(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m8,\s*ta,\s*mu\s+vsm\.v\s+(?:v[08]|v16|v= 24),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vsm_v_b1 )= ?} 1 } } */=0D +=0D +vbool2_t test_vlm_v_b2_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b2(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu\s+vlm\.v\s+(?:v[048]|v1[2= 6]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vl= m_v_b2 )?} 1 } } */=0D +=0D +void test_vsm_v_b2_32(uint8_t *base, vbool2_t value, size_t vl) {=0D + vsm_v_b2(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m4,\s*ta,\s*mu\s+vsm\.v\s+(?:v[048]|v1[2= 6]|v2[048]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: test_vs= m_v_b2 )?} 1 } } */=0D +=0D +vbool4_t test_vlm_v_b4_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b4(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu\s+vlm\.v\s+(?:v[02468]|v[= 1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vlm_v_b4 )?} 1 } } */=0D +=0D +void test_vsm_v_b4_32(uint8_t *base, vbool4_t value, size_t vl) {=0D + vsm_v_b4(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m2,\s*ta,\s*mu\s+vsm\.v\s+(?:v[02468]|v[= 1-2][02468]|v30),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vsm_v_b4 )?} 1 } } */=0D +=0D +vbool8_t test_vlm_v_b8_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b8(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1-= 2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vlm_v_b8 )?} 1 } } */=0D +=0D +void test_vsm_v_b8_32(uint8_t *base, vbool8_t value, size_t vl) {=0D + vsm_v_b8(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*m1,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1-= 2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: te= st_vsm_v_b8 )?} 1 } } */=0D +=0D +vbool16_t test_vlm_v_b16_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b16(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b16 )?} 1 } } */=0D +=0D +void test_vsm_v_b16_32(uint8_t *base, vbool16_t value, size_t vl) {=0D + vsm_v_b16(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf2,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b16 )?} 1 } } */=0D +=0D +vbool32_t test_vlm_v_b32_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b32(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b32 )?} 1 } } */=0D +=0D +void test_vsm_v_b32_32(uint8_t *base, vbool32_t value, size_t vl) {=0D + vsm_v_b32(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf4,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b32 )?} 1 } } */=0D +=0D +vbool64_t test_vlm_v_b64_32(const uint8_t *base, size_t vl) {=0D + return vlm_v_b64(base, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu\s+vlm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vlm_v_b64 )?} 1 } } */=0D +=0D +void test_vsm_v_b64_32(uint8_t *base, vbool64_t value, size_t vl) {=0D + vsm_v_b64(base, value, 32);=0D +}=0D +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*(?:ra|[sgtf]p|t[0-= 6]|s[0-9]|s10|s11|a[0-7]),\s*e8,\s*mf8,\s*ta,\s*mu\s+vsm\.v\s+(?:v[0-9]|v[1= -2][0-9]|v3[0-1]),\s*\((?:ra|[sgtf]p|t[0-6]|s[0-9]|s10|s11|a[0-7])\)\n(?: t= est_vsm_v_b64 )?} 1 } } */=0D -- =0D 2.36.1=0D =0D