From: shiyulong@iscas.ac.cn
To: gcc-patches@gcc.gnu.org
Cc: andrew@sifive.com, palmer@dabbelt.com, kito.cheng@gmail.com,
jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn,
jiawei@iscas.ac.cn, shihua@iscas.ac.cn, simon.cook@embecosm.com,
yulong <shiyulong@iscas.ac.cn>
Subject: [PATCH] RISC-V:Fix a bug that is the CMO builtins are missing parameter
Date: Mon, 6 Jun 2022 15:29:09 +0800 [thread overview]
Message-ID: <20220606072909.23673-1-shiyulong@iscas.ac.cn> (raw)
From: yulong <shiyulong@iscas.ac.cn>
We changed the RTL mode and builtins format about zicbom and zicboz subextensions.
gcc/ChangeLog:
* config/riscv/riscv-cmo.def (RISCV_BUILTIN): changed "RISCV_SI(DI)_FTYPE" to "RISCV_SI(DI)_FTPYE_SI(DI)"
* config/riscv/riscv-ftypes.def (0): deleted DEF_RISCV_FTYPE (0,(SI)) and DEF_RISCV_FTYPE (0,(DI))
* config/riscv/riscv.md: added a immediate_operand about cbo.clean, cbo.flush, cbo.inval and cbo.zero instructions
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbom-1.c: added a parameter
* gcc.target/riscv/cmo-zicbom-2.c: added a parameter
* gcc.target/riscv/cmo-zicboz-1.c: added a parameter
* gcc.target/riscv/cmo-zicboz-2.c: added a parameter
---
gcc/config/riscv/riscv-cmo.def | 16 ++++++++--------
gcc/config/riscv/riscv-ftypes.def | 2 --
gcc/config/riscv/riscv.md | 12 ++++++++----
gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 6 +++---
gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 6 +++---
gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 2 +-
7 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b30ecf96ec1..d43cbf62954 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -1,16 +1,16 @@
// zicbom
-RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32),
-RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64),
+RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, clean32),
+RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, clean64),
-RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32),
-RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64),
+RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, flush32),
+RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, flush64),
-RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32),
-RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64),
+RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, inval32),
+RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, inval64),
// zicboz
-RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32),
-RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64),
+RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, zero32),
+RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, zero64),
// zicbop
RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32),
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 62421292ce7..445eb8ee05d 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -28,7 +28,5 @@ along with GCC; see the file COPYING3. If not see
DEF_RISCV_FTYPE (0, (USI))
DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (0, (SI))
-DEF_RISCV_FTYPE (0, (DI))
DEF_RISCV_FTYPE (1, (SI, SI))
DEF_RISCV_FTYPE (1, (DI, DI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b8ab0cf169a..2d7d94eebd3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2893,28 +2893,32 @@
[(set_attr "length" "12")])
(define_insn "riscv_clean_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_CLEAN)]
"TARGET_ZICBOM"
"cbo.clean\t%a0"
)
(define_insn "riscv_flush_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_FLUSH)]
"TARGET_ZICBOM"
"cbo.flush\t%a0"
)
(define_insn "riscv_inval_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_INVAL)]
"TARGET_ZICBOM"
"cbo.inval\t%a0"
)
(define_insn "riscv_zero_<mode>"
- [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+ [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")
+ (match_operand:X 1 "immediate_operand" "i")]
UNSPECV_ZERO)]
"TARGET_ZICBOZ"
"cbo.zero\t%a0"
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
index e2ba2183511..eb68944418b 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c
@@ -3,17 +3,17 @@
int foo1()
{
- return __builtin_riscv_zicbom_cbo_clean();
+ return __builtin_riscv_zicbom_cbo_clean(0);
}
int foo2()
{
- return __builtin_riscv_zicbom_cbo_flush();
+ return __builtin_riscv_zicbom_cbo_flush(0);
}
int foo3()
{
- return __builtin_riscv_zicbom_cbo_inval();
+ return __builtin_riscv_zicbom_cbo_inval(0);
}
/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
index a605e8b1bdc..3dc0f6d3368 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c
@@ -3,17 +3,17 @@
int foo1()
{
- return __builtin_riscv_zicbom_cbo_clean();
+ return __builtin_riscv_zicbom_cbo_clean(0);
}
int foo2()
{
- return __builtin_riscv_zicbom_cbo_flush();
+ return __builtin_riscv_zicbom_cbo_flush(0);
}
int foo3()
{
- return __builtin_riscv_zicbom_cbo_inval();
+ return __builtin_riscv_zicbom_cbo_inval(0);
}
/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
index 96c1674ef2d..4726577f119 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c
@@ -3,7 +3,7 @@
int foo1()
{
- return __builtin_riscv_zicboz_cbo_zero();
+ return __builtin_riscv_zicboz_cbo_zero(0);
}
/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
index 9d99839b1e7..18d66b88515 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c
@@ -3,7 +3,7 @@
int foo1()
{
- return __builtin_riscv_zicboz_cbo_zero();
+ return __builtin_riscv_zicboz_cbo_zero(0);
}
/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */
--
2.17.1
next reply other threads:[~2022-06-06 7:29 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 7:29 shiyulong [this message]
2022-06-06 9:05 ` Kito Cheng
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