From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id B775E3847814 for ; Thu, 30 Jun 2022 01:50:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B775E3847814 X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="270980847" X-IronPort-AV: E=Sophos;i="5.92,232,1650956400"; d="scan'208";a="270980847" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 18:50:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,232,1650956400"; d="scan'208";a="680768715" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by FMSMGA003.fm.intel.com with ESMTP; 29 Jun 2022 18:50:31 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 40E7610056AE; Thu, 30 Jun 2022 09:50:31 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] i386: Add AVX512BW to AVX512F in MASK_ISA2 Date: Thu, 30 Jun 2022 09:50:31 +0800 Message-Id: <20220630015031.104897-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Jun 2022 01:50:37 -0000 Hi all, I just found in MASK_ISA2_UNSET part, since AVX512BW is based on AVX512F, we should add OPTION_MASK_ISA2_AVX512BW_UNSET to AVX512F for maintainence convenience and logic correctness, or we will need to add all future ISAs based on AVX512BW in both AVX512F and AVX512BW. This will be easily forgot and might cause confusion. Also remove the redundant ones in this change. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX512F_UNSET): Add OPTION_MASK_ISA2_AVX512BW_UNSET, remove OPTION_MASK_ISA2_AVX512BF16_UNSET and OPTION_MASK_ISA2_AVX512FP16_UNSET. --- gcc/common/config/i386/i386-common.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index cb878163492..c0c2ad74d87 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -315,11 +315,10 @@ along with GCC; see the file COPYING3. If not see | OPTION_MASK_ISA_SSE_UNSET) #define OPTION_MASK_ISA2_AVX512F_UNSET \ - (OPTION_MASK_ISA2_AVX512BF16_UNSET \ + (OPTION_MASK_ISA2_AVX512BW_UNSET \ | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ - | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \ - | OPTION_MASK_ISA2_AVX512FP16_UNSET) + | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ OPTION_MASK_ISA2_SSE_UNSET #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET -- 2.18.1