From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dedi548.your-server.de (dedi548.your-server.de [85.10.215.148]) by sourceware.org (Postfix) with ESMTPS id D863C3835690 for ; Fri, 22 Jul 2022 13:02:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D863C3835690 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embedded-brains.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embedded-brains.de Received: from sslproxy03.your-server.de ([88.198.220.132]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oEsIw-000ImN-15 for gcc-patches@gcc.gnu.org; Fri, 22 Jul 2022 15:02:54 +0200 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy03.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1oEsIw-000CeD-79 for gcc-patches@gcc.gnu.org; Fri, 22 Jul 2022 15:02:54 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id DB56648001C for ; Fri, 22 Jul 2022 15:02:53 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id M7KZe5PTntb9 for ; Fri, 22 Jul 2022 15:02:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 5EDA64801BF for ; Fri, 22 Jul 2022 15:02:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id YbjksnEkIzcy for ; Fri, 22 Jul 2022 15:02:53 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [192.168.96.242]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 33AFC48001C for ; Fri, 22 Jul 2022 15:02:53 +0200 (CEST) From: Sebastian Huber To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] Allow subtarget customization of CC1_SPEC Date: Fri, 22 Jul 2022 15:02:49 +0200 Message-Id: <20220722130250.59766-1-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authenticated-Sender: smtp-embedded@poldinet.de X-Virus-Scanned: Clear (ClamAV 0.103.6/26609/Fri Jul 22 09:56:47 2022) X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jul 2022 13:03:06 -0000 gcc/ChangeLog: * gcc.cc (SUBTARGET_CC1_SPEC): Define if not defined. (CC1_SPEC): Define to SUBTARGET_CC1_SPEC. * config/arm/arm.h (CC1_SPEC): Remove. * config/arc/arc.h (CC1_SPEC): Append SUBTARGET_CC1_SPEC. * config/cris/cris.h (CC1_SPEC): Likewise. * config/frv/frv.h (CC1_SPEC): Likewise. * config/i386/i386.h (CC1_SPEC): Likewise. * config/ia64/ia64.h (CC1_SPEC): Likewise. * config/lm32/lm32.h (CC1_SPEC): Likewise. * config/m32r/m32r.h (CC1_SPEC): Likewise. * config/mcore/mcore.h (CC1_SPEC): Likewise. * config/microblaze/microblaze.h: Likewise. * config/nds32/nds32.h (CC1_SPEC): Likewise. * config/nios2/nios2.h (CC1_SPEC): Likewise. * config/pa/pa.h (CC1_SPEC): Likewise. * config/rs6000/sysv4.h (CC1_SPEC): Likewise. * config/rx/rx.h (CC1_SPEC): Likewise. * config/sparc/sparc.h (CC1_SPEC): Likewise. --- gcc/config/arc/arc.h | 3 ++- gcc/config/arm/arm.h | 4 ---- gcc/config/cris/cris.h | 3 ++- gcc/config/frv/frv.h | 2 +- gcc/config/i386/i386.h | 2 +- gcc/config/ia64/ia64.h | 2 +- gcc/config/lm32/lm32.h | 2 +- gcc/config/m32r/m32r.h | 2 +- gcc/config/mcore/mcore.h | 2 +- gcc/config/microblaze/microblaze.h | 3 ++- gcc/config/nds32/nds32.h | 2 +- gcc/config/nios2/nios2.h | 2 +- gcc/config/pa/pa.h | 2 +- gcc/config/rs6000/sysv4.h | 3 ++- gcc/config/rx/rx.h | 3 ++- gcc/config/sparc/sparc.h | 2 +- gcc/gcc.cc | 8 +++++++- 17 files changed, 27 insertions(+), 20 deletions(-) diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 539a1662084..177287b11aa 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -68,7 +68,8 @@ along with GCC; see the file COPYING3. If not see #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \ %{EB:-mbig-endian} %{EL:-mlittle-endian} \ %{G*} \ -" +" \ +SUBTARGET_CC1_SPEC extern const char *arc_cpu_to_as (int argc, const char **argv); =20 #define EXTRA_SPEC_FUNCTIONS \ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f479540812a..24fdf7fde23 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -91,10 +91,6 @@ extern tree arm_bf16_ptr_type_node; #undef CPP_SPEC #define CPP_SPEC "%(subtarget_cpp_spec)" =20 -#ifndef CC1_SPEC -#define CC1_SPEC "" -#endif - /* This macro defines names of additional specifications to put in the s= pecs that can be used in various specifications like CC1_SPEC. Its defini= tion is an initializer with a subgrouping for each command option. diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h index 6edfe13d92c..ed89b3fa6b0 100644 --- a/gcc/config/cris/cris.h +++ b/gcc/config/cris/cris.h @@ -135,7 +135,8 @@ extern int cris_cpu_version; %{metrax100:-march=3Dv8}\ %{march=3D*:-march=3D%*}\ %{mcpu=3D*:-mcpu=3D%*}\ - %(cc1_subtarget)" + %(cc1_subtarget)" \ + SUBTARGET_CC1_SPEC =20 /* For the cris-*-elf subtarget. */ #define CRIS_CC1_SUBTARGET_SPEC \ diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h index 8cd67f75b09..b0f39ee238e 100644 --- a/gcc/config/frv/frv.h +++ b/gcc/config/frv/frv.h @@ -115,7 +115,7 @@ =20 Do not define this macro if it does not need to do anything. */ /* For ABI compliance, we need to put bss data into the normal data sect= ion. */ -#define CC1_SPEC "%{G*}" +#define CC1_SPEC "%{G*}" SUBTARGET_CC1_SPEC =20 #undef LINK_SPEC #define LINK_SPEC "\ diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index f16df633e84..f1ceb6b2557 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -614,7 +614,7 @@ extern const char *host_detect_local_cpu (int argc, c= onst char **argv); #define TARGET_D_HAS_STDCALL_CONVENTION ix86_d_has_stdcall_convention =20 #ifndef CC1_SPEC -#define CC1_SPEC "%(cc1_cpu) " +#define CC1_SPEC "%(cc1_cpu) " SUBTARGET_CC1_SPEC #endif =20 /* This macro defines names of additional specifications to put in the diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h index bd0ef35e9a4..0e11cef0edc 100644 --- a/gcc/config/ia64/ia64.h +++ b/gcc/config/ia64/ia64.h @@ -51,7 +51,7 @@ do { \ { "asm_extra", ASM_EXTRA_SPEC }, \ SUBTARGET_EXTRA_SPECS =20 -#define CC1_SPEC "%(cc1_cpu) " +#define CC1_SPEC "%(cc1_cpu) " SUBTARGET_CC1_SPEC =20 #define ASM_EXTRA_SPEC "" =20 diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h index 23f66c90446..65a9141cd94 100644 --- a/gcc/config/lm32/lm32.h +++ b/gcc/config/lm32/lm32.h @@ -63,7 +63,7 @@ #define LIB_SPEC "%{!T*:-T sim.ld}" =20 #undef CC1_SPEC -#define CC1_SPEC "%{G*}" +#define CC1_SPEC "%{G*}" SUBTARGET_CC1_SPEC =20 /*---------------------------------*/ /* Target machine storage layout. */ diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index b96eec8fe3f..38632683152 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -155,7 +155,7 @@ #define CPP_SPEC "%(cpp_cpu)" =20 #undef CC1_SPEC -#define CC1_SPEC "%{G*} %(cc1_cpu)" +#define CC1_SPEC "%{G*} %(cc1_cpu)" SUBTARGET_CC1_SPEC =20 /* Options to pass on to the assembler. */ #undef ASM_SPEC diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index c905c4024f3..1a11d651b72 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -82,7 +82,7 @@ extern char * mcore_current_function_name; =20 /* The MCore ABI says that bitfields are unsigned by default. */ -#define CC1_SPEC "-funsigned-bitfields" +#define CC1_SPEC "-funsigned-bitfields" SUBTARGET_CC1_SPEC =20 /* Target machine storage Layout. */ =20 diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/m= icroblaze.h index d28bc766de8..7ace9a07cfe 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -119,7 +119,8 @@ extern enum pipeline_type microblaze_pipe; %{G*} \ %(subtarget_cc1_spec) \ %{mxl-multiply-high:-mcpu=3Dv6.00.a} \ -" +" \ +SUBTARGET_CC1_SPEC #endif =20 #define EXTRA_SPECS \ diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h index 18ef8ae9ee8..55366f0d29f 100644 --- a/gcc/config/nds32/nds32.h +++ b/gcc/config/nds32/nds32.h @@ -962,7 +962,7 @@ enum nds32_builtins {"float", "%{!mfloat-abi=3D*:-mfloat-abi=3D%(VALUE)}" } =20 #define CC1_SPEC \ - NDS32_EXT_DSP_SPEC + NDS32_EXT_DSP_SPEC SUBTARGET_CC1_SPEC =20 #define ASM_SPEC \ " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ diff --git a/gcc/config/nios2/nios2.h b/gcc/config/nios2/nios2.h index 7c7d5c05fd7..60b052b945b 100644 --- a/gcc/config/nios2/nios2.h +++ b/gcc/config/nios2/nios2.h @@ -58,7 +58,7 @@ #define OPTION_DEFAULT_SPECS \ {"arch", "%{!march=3D*:%{!mcpu=3D*:-march=3D%(VALUE)}}" } =20 -#define CC1_SPEC "%{G*}" +#define CC1_SPEC "%{G*}" SUBTARGET_CC1_SPEC =20 #if TARGET_ENDIAN_DEFAULT =3D=3D 0 # define ASM_SPEC "%{!meb:-EL} %{meb:-EB} %{march=3D*:-march=3D%*}" diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 92d3d1841a9..dc14d5c0561 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -202,7 +202,7 @@ do { \ } \ while (0) =20 -#define CC1_SPEC "%{pg:} %{p:}" +#define CC1_SPEC "%{pg:} %{p:}" SUBTARGET_CC1_SPEC =20 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}" =20 diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 7e2519de5d4..a6791654a5a 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -585,7 +585,8 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDI= AN) %{msdata: -msdata=3Ddefault} \ %{mno-sdata: -msdata=3Dnone} \ %{!mbss-plt: %{!msecure-plt: %(cc1_secure_plt_default)}}" \ -GNU_USER_TARGET_CC1_SPEC +GNU_USER_TARGET_CC1_SPEC \ +SUBTARGET_CC1_SPEC =20 /* Default starting address if specified. */ #define LINK_START_SPEC "\ diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h index ce9c2ff1278..eff426aa9e3 100644 --- a/gcc/config/rx/rx.h +++ b/gcc/config/rx/rx.h @@ -79,7 +79,8 @@ #define CC1_SPEC "\ %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwar= f}} \ %{mcpu=3Drx100:%{fpu:%erx100 cpu does not have FPU hardware}} \ - %{mcpu=3Drx200:%{fpu:%erx200 cpu does not have FPU hardware}}" + %{mcpu=3Drx200:%{fpu:%erx200 cpu does not have FPU hardware}}" \ + SUBTARGET_CC1_SPEC =20 #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s" diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 2e17fca197a..149de720367 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -327,7 +327,7 @@ along with GCC; see the file COPYING3. If not see /* This used to translate -dalign to -malign, but that is no good because it can't turn off the usual meaning of making debugging dumps= . */ =20 -#define CC1_SPEC "" +#define CC1_SPEC SUBTARGET_CC1_SPEC =20 /* Override in target specific files. */ #define ASM_CPU_SPEC "\ diff --git a/gcc/gcc.cc b/gcc/gcc.cc index 5cbb38560b2..abc076fe233 100644 --- a/gcc/gcc.cc +++ b/gcc/gcc.cc @@ -703,10 +703,16 @@ proper position among the other output files. */ #define CPP_SPEC "" #endif =20 +/* Subtargets can define SUBTARGET_CC1_SPEC to provide extra args to cc1= and + cc1plus or extra switch-translations. */ +#ifndef SUBTARGET_CC1_SPEC +#define SUBTARGET_CC1_SPEC "" +#endif + /* config.h can define CC1_SPEC to provide extra args to cc1 and cc1plus or extra switch-translations. */ #ifndef CC1_SPEC -#define CC1_SPEC "" +#define CC1_SPEC SUBTARGET_CC1_SPEC #endif =20 /* config.h can define CC1PLUS_SPEC to provide extra args to cc1plus --=20 2.35.3