From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: rguenther@suse.de, jakub@redhat.com, palmer@rivosinc.com,
kito.cheng@gmail.com, jim.wilson.gcc@gmail.com,
wuwei2016@iscas.ac.cn, jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works
Date: Thu, 28 Jul 2022 11:25:44 +0800 [thread overview]
Message-ID: <20220728032544.2571608-1-jiawei@iscas.ac.cn> (raw)
This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.
gcc/testsuite/ChangeLog:
* gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
---
gcc/testsuite/gcc.dg/pr106397.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..19274fa8771 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,8 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param prefetch-latency=3 -fprefetch-loop-arrays" } */
/* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */
+/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */
+/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */
int
bar (void)
--
2.25.1
next reply other threads:[~2022-07-28 3:26 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-28 3:25 jiawei [this message]
2022-07-28 7:45 ` Richard Biener
2022-07-28 9:28 ` jiawei
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