From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 8A216385801C; Wed, 10 Aug 2022 07:11:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8A216385801C Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27A67X5c021725; Wed, 10 Aug 2022 07:11:31 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3hv4c6nd4a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Aug 2022 07:11:30 +0000 Received: from m0098420.ppops.net (m0098420.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 27A6Uvif030016; Wed, 10 Aug 2022 07:11:30 GMT Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3hv4c6nd37-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Aug 2022 07:11:30 +0000 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 27A77EYh013574; Wed, 10 Aug 2022 07:11:27 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma03fra.de.ibm.com with ESMTP id 3huwvfrcme-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Aug 2022 07:11:27 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27A7BPGb26345894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 10 Aug 2022 07:11:25 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 36B6FA4040; Wed, 10 Aug 2022 07:11:25 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C92DA4057; Wed, 10 Aug 2022 07:11:24 +0000 (GMT) Received: from pike.rch.stglabs.ibm.com (unknown [9.5.12.127]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 10 Aug 2022 07:11:24 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, guojiufu@linux.ibm.com Subject: [PATCH] rs6000: Enable generate const through pli+pli+rldimi Date: Wed, 10 Aug 2022 15:11:23 +0800 Message-Id: <20220810071123.165157-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ygkYEW3CTUiW_znuT7ankZ0KRM-s7NnL X-Proofpoint-GUID: qjgHfi_itH8biWfabtNqPdu2KGYaJ4bT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-10_01,2022-08-09_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 mlxscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208100019 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Aug 2022 07:11:33 -0000 Hi, As mentioned in PR106550, since pli could support 34bits immediate, we could use less instructions(3insn would be ok) to build 64bits constant with pli. For example, for constant 0x020805006106003, we could generate it with: asm code1: pli 9,101736451 (0x6106003) sldi 9,9,32 paddi 9,9, 2130000 (0x0208050) or asm code2: pli 10, 2130000 pli 9, 101736451 rldimi 9, 10, 32, 0 If there is only one register can be used, then the asm code1 is ok. Otherwise asm code2 may be better. This patch re-enable the constant building(splitter) before RA by updating the constrains from int_reg_operand_not_pseudo to gpc_reg_operand. And then, we could use two different pseduo for two pli(s), and asm code2 can be generated. This patch also could generate asm code1 if hard register is allocated for the constant. This patch pass boostrap and regtest on ppc64le(includes p10). Is it ok for trunk? BR, Jeff(Jiufu) PR target/106550 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Enable constant build with pli instructions. * config/rs6000/rs6000.md: Use gpc_reg_operand for constant splitter. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr106550.c: New test. --- gcc/config/rs6000/rs6000.cc | 40 +++++++++++++++++++++ gcc/config/rs6000/rs6000.md | 2 +- gcc/testsuite/gcc.target/powerpc/pr106550.c | 14 ++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr106550.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index df491bee2ea..a2e6b7f59a0 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10181,6 +10181,46 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) gen_rtx_IOR (DImode, copy_rtx (temp), GEN_INT (ud1))); } + else if (TARGET_PREFIXED) + { + /* pli 9,high32 + pli 10,low32 + rldimi 9,10,32,0. */ + if (can_create_pseudo_p ()) + { + temp = gen_reg_rtx (DImode); + rtx temp1 = gen_reg_rtx (DImode); + emit_move_insn (copy_rtx (temp), GEN_INT ((ud4 << 16) | ud3)); + emit_move_insn (copy_rtx (temp1), GEN_INT ((ud2 << 16) | ud1)); + + rtx one = gen_rtx_AND (DImode, temp1, GEN_INT (0xffffffff)); + rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32)); + emit_move_insn (dest, gen_rtx_IOR (DImode, one, two)); + } + + /* pli 9,high32 + sldi 9,32 + paddi 9,9,low32. */ + else + { + emit_move_insn (copy_rtx (dest), GEN_INT ((ud4 << 16) | ud3)); + + emit_move_insn (copy_rtx (dest), + gen_rtx_ASHIFT (DImode, copy_rtx (dest), + GEN_INT (32))); + + bool cannot_use_paddi = REGNO (dest) == FIRST_GPR_REGNO; + + /* Use paddi for the low32 bits. */ + if (ud2 != 0 && ud1 != 0 && !cannot_use_paddi) + emit_move_insn (dest, gen_rtx_PLUS (DImode, copy_rtx (dest), + GEN_INT ((ud2 << 16) | ud1))); + /* Use oris, ori for low32 bits. */ + if (ud2 != 0 && (ud1 == 0 || cannot_use_paddi)) + emit_move_insn (ud1 != 0 ? copy_rtx (dest) : dest, + gen_rtx_IOR (DImode, copy_rtx (dest), + GEN_INT (ud2 << 16))); + if (ud1 != 0 && (ud2 == 0 || cannot_use_paddi)) + emit_move_insn (dest, gen_rtx_IOR (DImode, copy_rtx (dest), + GEN_INT (ud1))); + } + } else { temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1367a2cb779..abe777a593c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9659,7 +9659,7 @@ (define_split ;; When non-easy constants can go in the TOC, this should use ;; easy_fp_constant predicate. (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + [(set (match_operand:DI 0 "gpc_reg_operand") (match_operand:DI 1 "const_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550.c b/gcc/testsuite/gcc.target/powerpc/pr106550.c new file mode 100644 index 00000000000..bca7760bad9 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr106550.c @@ -0,0 +1,14 @@ +/* PR target/106550 */ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -std=c99 -mdejagnu-cpu=power10" } */ + +void +foo (unsigned long long *a) +{ + *a++ = 0x020805006106003; + *a++ = 0x2351847027482577; +} + +/* { dg-final { scan-assembler-times {\mpli\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ + -- 2.17.1