From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id 78C40385829A for ; Wed, 10 Aug 2022 17:39:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 78C40385829A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 27AHcqPj014978; Wed, 10 Aug 2022 12:38:52 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 27AHcqUN014977; Wed, 10 Aug 2022 12:38:52 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Wed, 10 Aug 2022 12:38:52 -0500 From: Segher Boessenkool To: HAO CHEN GUI Cc: gcc-patches , David , "Kewen.Lin" , Peter Bergner Subject: Re: [PATCH v3] Modify combine pattern by a pseudo AND with its nonzero bits [PR93453] Message-ID: <20220810173852.GC25951@gate.crashing.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, JMQ_SPF_NEUTRAL, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Aug 2022 17:39:54 -0000 Hi! Sorry for the tardiness. On Fri, Jul 22, 2022 at 03:07:55PM +0800, HAO CHEN GUI wrote: > This patch creates a new function - change_pseudo_and_mask. If recog fails, > the function converts a single pseudo to the pseudo AND with a mask if the > outer operator is IOR/XOR/PLUS and inner operator is ASHIFT or AND. The > conversion helps pattern to match rotate and mask insn on some targets. The name isn't so clear. It isn't changing a mask, to start with. > +/* When the outer code of set_src is IOR/XOR/PLUS and the inner code is > + ASHIFT/AND, "When the outercode of the SET_SRC of PAT is ..." > convert a pseudo to pseudo AND with a mask if its nonzero_bits > + is less than its mode mask. The nonzero_bits in later passes is not a > + superset of what is known in combine pass. So an insn with nonzero_bits > + can't be recoged later. */ Can this not be done with a splitter in the machine description? Segher