From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id E359B3858C54 for ; Fri, 2 Sep 2022 15:57:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E359B3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 282Fu5fe015610; Fri, 2 Sep 2022 10:56:05 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 282Fu5Nl015609; Fri, 2 Sep 2022 10:56:05 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Fri, 2 Sep 2022 10:56:04 -0500 From: Segher Boessenkool To: HAO CHEN GUI Cc: gcc-patches , David , "Kewen.Lin" , Peter Bergner Subject: Re: [PATCH v2, rs6000] Change insn condition from TARGET_64BIT to TARGET_POWERPC64 for VSX scalar extract/insert instructions Message-ID: <20220902155604.GO25951@gate.crashing.org> References: <3cd458bc-b01f-cc61-241a-f12d6a49bc87@linux.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3cd458bc-b01f-cc61-241a-f12d6a49bc87@linux.ibm.com> User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,JMQ_SPF_NEUTRAL,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi! On Fri, Sep 02, 2022 at 04:31:38PM +0800, HAO CHEN GUI wrote: > This patch is for internal issue1136. This isn't useful to most people. Either just don't mention it here, or make a public PR for it if that is useful? > It changes insn condition from > TARGET_64BIT to TARGET_POWERPC64 for VSX scalar extract/insert instructions. > These instructions all use DI registers and can be invoked with -mpowerpc64 > in a 32-bit environment. > gcc/ > * config/rs6000/vsx.md (xsxexpdp): Change insn condition from > TARGET_64BIT to TARGET_POWERPC64. > (xsxsigdp): Likewise. > (xsiexpdp): Likewise. > (xsiexpdpf): Likewise. > > gcc/testsuite/ > * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Change effective > target from lp64 to has_arch_ppc64 and add -mpowerpc64 for 32-bit > environment. > * gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-exp-7.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-7.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. > - const signed long __builtin_vsx_scalar_extract_exp (double); > + const unsigned long long __builtin_vsx_scalar_extract_exp (double); > VSEEDP xsxexpdp {} > > - const signed long __builtin_vsx_scalar_extract_sig (double); > + const unsigned long long __builtin_vsx_scalar_extract_sig (double); > VSESDP xsxsigdp {} This also brings these legacy builtins in line with the vec_ versions, which are the preferred builtins (they are defined in the PVIPR). > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -5098,7 +5098,7 @@ (define_insn "xsxexpdp" > [(set (match_operand:DI 0 "register_operand" "=r") > (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] > UNSPEC_VSX_SXEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR && TARGET_POWERPC64" > "xsxexpdp %0,%x1" > [(set_attr "type" "integer")]) This doesn't need POWERPC64 even -- instead, it could use :GPR instead of :DI, the output is always tiny. > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > @@ -1,7 +1,8 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile { target { powerpc*-*-linux* } } } */ Why? > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-additional-options "-mpowerpc64" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ This is guaranteed already by that -mpowerpc64. It probably is best if you do not add -mpowerpc64 at all. That solves both problems, is simpler, and gives better coverage as well :-) So just use has_arch_ppc64 instead of lp64. That makes it run on a strict superset of cases :-) > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run { target { powerpc*-*-linux* } } } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ Nothing in gcc.target/powerpc has to check for powerpc*-*-* at all. If you want to test for linux (you shouldn't here afaics?), that is just *-*-linux* . Segher