From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by sourceware.org (Postfix) with ESMTP id 4A2513858C53; Fri, 2 Sep 2022 16:21:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4A2513858C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=kernel.crashing.org Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 282GKU61016844; Fri, 2 Sep 2022 11:20:30 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 282GKU2q016843; Fri, 2 Sep 2022 11:20:30 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Fri, 2 Sep 2022 11:20:30 -0500 From: Segher Boessenkool To: Peter Bergner Cc: Jiufu Guo , meissner@linux.ibm.com, gcc-patches@gcc.gnu.org, linkw@gcc.gnu.org, dje.gcc@gmail.com Subject: Re: [PATCH 1/2] Using pli(paddi) and rotate to build 64bit constants Message-ID: <20220902162030.GR25951@gate.crashing.org> References: <20220901032400.23692-1-guojiufu@linux.ibm.com> <20220901215233.GJ25951@gate.crashing.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,JMQ_SPF_NEUTRAL,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Sep 02, 2022 at 10:29:35AM -0500, Peter Bergner wrote: > On 9/1/22 4:52 PM, Segher Boessenkool wrote: > > On Thu, Sep 01, 2022 at 11:24:00AM +0800, Jiufu Guo wrote: > >> As mentioned in PR106550, since pli could support 34bits immediate, we could > >> use less instructions(3insn would be ok) to build 64bits constant with pli. > > > >> For example, for constant 0x020805006106003, we could generate it with: > >> asm code1: > >> pli 9,101736451 (0x6106003) > >> sldi 9,9,32 > >> paddi 9,9, 2130000 (0x0208050) > > > > 3 insns, 2 insns dependent on the previous, each. > > > >> or asm code2: > >> pli 10, 2130000 > >> pli 9, 101736451 > >> rldimi 9, 10, 32, 0 > > > > 3 insns, 1 insn dependent on both others. > > Yeah, the improvement here is the fewer dependent instructions, since > 2 64-bit + 1 32-bit instructions is the same size as 5 32-bit insns. It also helps CSE if you do say 0x1200aa00bb0034 and 0x1200aa00bb0056, or even just 0x1200aa001200aa maybe (we probably have a separate pattern for the latter though :-) ) Segher