From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 2E48F3858D32 for ; Mon, 5 Sep 2022 02:43:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2E48F3858D32 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662345802; x=1693881802; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=x3YFA1HlUMx1m3xcE5ecIbbg4m4xkVrtJH7Gnkga4xg=; b=DgqjomTu+OdrQjypY6FnFhn7T0B/wI2UXj739QhrRKs15BQlOkMTSZ/1 qugl+r605Pnvd3dJdCbl31xulQIjOF4Qro1nqabs7Xl1ptUHI74LGqbnx WZppMunzdO3hkOJR77en87sjC4Ide5bKxWvLb9zit7rqpuKlNQiqpBolL nM1kQD0NIGtMCD5Kv8wfGp9dH6A5QRFgwOOnHBmVMfr1+8udTe0ryG2sM jUGIJ22R6oEjKeEWQZTNezMKfIJbvfeMJ+LAcOU10eaPB3wcQvGXafdzp nB/iLJzfmxfUaoysuoKIbaTz7abn2F57JHP53v9fj897hqYlb5KMwIDZw Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10460"; a="276034229" X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="276034229" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2022 19:43:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="789232234" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 04 Sep 2022 19:43:18 -0700 Received: from shliclel4051.sh.intel.com (shliclel4051.sh.intel.com [10.239.240.51]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 262E9100567F; Mon, 5 Sep 2022 10:43:18 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Fix _mm512_cvt_roundps_ph to generate sae instruction. Date: Mon, 5 Sep 2022 10:43:18 +0800 Message-Id: <20220905024318.1259282-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: zmm-version vcvtps2ph is special, it encodes {sae} in evex, but put round control in the imm. For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae} and round control, we need to separate it in the assembly output since vcvtps2ph will ignore imm[3:7]. Corresponding llvm patch. Intrinsic guide will also be updated in the next version. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ready to install. gcc/ChangeLog: * config/i386/i386-builtin.def (IX86_BUILTIN_CVTPS2PH512): Map to CODE_FOR_avx512f_vcvtps2ph512_mask_sae. * config/i386/sse.md (avx512f_vcvtps2ph512): Extend to .. (avx512f_vcvtps2ph512): .. this. (avx512f_vcvtps2ph512_mask_sae): New expander gcc/testsuite/ChangeLog: * gcc.target/i386/avx512f-vcvtps2ph-sae.c: New test. --- gcc/config/i386/i386-builtin.def | 2 +- gcc/config/i386/sse.md | 30 +++++++++++++++++-- .../gcc.target/i386/avx512f-vcvtps2ph-sae.c | 18 +++++++++++ 3 files changed, 47 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index f9c7abde2cf..dea52a28d28 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -1351,7 +1351,7 @@ BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) -BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) +BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_avx512f_vcvtps2ph512_mask_sae, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT) BDESC (OPTION_MASK_ISA_AVX512F, 0, CODE_FOR_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 259048481b6..a35b0d368e6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -26902,14 +26902,40 @@ (define_insn "*vcvtps2ph256" (set_attr "btver2_decode" "vector") (set_attr "mode" "V8SF")]) -(define_insn "avx512f_vcvtps2ph512" +;; vcvtps2ph is special, it encodes {sae} in evex, but round control in the imm +;; For intrinsic _mm512_cvt_roundps_ph (a, imm), imm contains both {sae} +;; and round control, we need to separate it in the assembly output. +;; op2 in avx512f_vcvtps2ph512_mask_sae contains both sae and round control. +(define_expand "avx512f_vcvtps2ph512_mask_sae" + [(set (match_operand:V16HI 0 "register_operand" "=v") + (vec_merge:V16HI + (unspec:V16HI + [(match_operand:V16SF 1 "register_operand" "v") + (match_operand:SI 2 "const_0_to_255_operand")] + UNSPEC_VCVTPS2PH) + (match_operand:V16HI 3 "nonimm_or_0_operand") + (match_operand:HI 4 "register_operand")))] + "TARGET_AVX512F" +{ + int round = INTVAL (operands[2]); + /* Separate {sae} from rounding control imm, + imm[3:7] will be ignored by the instruction. */ + if (round & 8) + { + emit_insn (gen_avx512f_vcvtps2ph512_mask_round (operands[0], operands[1], + operands[2], operands[3], operands[4], GEN_INT (8))); + DONE; + } +}) + +(define_insn "avx512f_vcvtps2ph512" [(set (match_operand:V16HI 0 "register_operand" "=v") (unspec:V16HI [(match_operand:V16SF 1 "register_operand" "v") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_AVX512F" - "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" + "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "ssecvt") (set_attr "prefix" "evex") (set_attr "mode" "V16SF")]) diff --git a/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c new file mode 100644 index 00000000000..e0714d437d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-sae.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f" } */ +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\{\n\]*\{sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512 x; +volatile __m256i y; + +void extern +avx512f_test (void) +{ + y = _mm512_cvtps_ph (x, 8); + y = _mm512_maskz_cvtps_ph (4, x, 9); + y = _mm512_mask_cvtps_ph (y, 2, x, 10); +} -- 2.27.0