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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id bt24-20020a056000081800b0022377df817fsm10394967wrb.58.2022.09.05.14.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Sep 2022 14:44:43 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt , Vineet Gupta , Jojo R , Christoph Muellner , Kito Cheng , Philipp Tomsich Subject: [PATCH] riscv: implement TARGET_MODE_REP_EXTENDED Date: Mon, 5 Sep 2022 23:44:37 +0200 Message-Id: <20220905214437.1275139-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: TARGET_MODE_REP_EXTENDED is supposed to match LOAD_EXTEND_OP, so this adds an implementation using the same logic as in LOAD_EXTEND_OP. This reduces the number of extension operations, as evidenced in the reduction of dynamic instructions for the xz benchmark in SPEC CPU: # dynamic instructions baseline new improvement xz, workload 1 384681308026 374464538911 2.66% xz, workload 2 985995327109 974304030498 1.19% xz, workload 3 545372994523 533717744260 2.14% The shift-shift-2.c testcase needs to be adjusted, as it will no longer use slliw/slriw for sub5, but will instead emit slli/slri. No new regressions runnung the riscv.exp suite. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_mode_rep_extended): (TARGET_MODE_REP_EXTENDED): Implement. gcc/testsuite/ChangeLog: * gcc.target/riscv/shift-shift-2.c: Adjust. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.cc | 15 +++++++++++++++ gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 2 -- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 675d92c0961..cf829f390ab 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5053,6 +5053,18 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return true; } +/* Implement TARGET_MODE_REP_EXTENDED. */ + +static int +riscv_mode_rep_extended (scalar_int_mode mode, scalar_int_mode mode_rep) +{ + /* On 64-bit targets, SImode register values are sign-extended to DImode. */ + if (TARGET_64BIT && mode == SImode && mode_rep == DImode) + return SIGN_EXTEND; + + return UNKNOWN; +} + /* Implement TARGET_MODES_TIEABLE_P. Don't allow floating-point modes to be tied, since type punning of @@ -6153,6 +6165,9 @@ riscv_init_libfuncs (void) #undef TARGET_HARD_REGNO_MODE_OK #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok +#undef TARGET_MODE_REP_EXTENDED +#define TARGET_MODE_REP_EXTENDED riscv_mode_rep_extended + #undef TARGET_MODES_TIEABLE_P #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index 5f93be15ac5..2f38b3f0fec 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -38,5 +38,3 @@ sub5 (unsigned int i) } /* { dg-final { scan-assembler-times "slli" 5 } } */ /* { dg-final { scan-assembler-times "srli" 5 } } */ -/* { dg-final { scan-assembler-times "slliw" 1 } } */ -/* { dg-final { scan-assembler-times "srliw" 1 } } */ -- 2.34.1