From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id 74D37385140B for ; Tue, 6 Sep 2022 10:40:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 74D37385140B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wr1-x429.google.com with SMTP id b5so14786106wrr.5 for ; Tue, 06 Sep 2022 03:40:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=kgefZrPhgt8si1dWWEiJcF9xnM5DhX29IwYwPrXmfWU=; b=C7GxuE34pbIkY8C2FYhnlfP3hQmHhB5WdSILoIkWVSmocgc8ft0iZlQJaAAHOkksnF 0vmEIvvftH0ug2cSDrtCN6Pl2ER85ZQexdzSxBvRd6cta7CzHsxVMdKRUrsAiyRgdLU8 J1ehasV/QQSTaPQJkBK/vD6ZUBNxtE+CmsH5cxMapmgsjk/ez3bfR8XrJ3Q/WDQR0y1M 0+ehwoOFCG9wnM6ZhHVrU5car0hpbwX2443tfRtk/10rDa3ZOZTFG1TOUYpJ6EwMHCGs 6TxnWmH+CPyhXddsxhRLdjDVZoo0jrnPp3Giy0mTLjKkscYaAGOvm97dnxEpNsttBJA+ RxUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=kgefZrPhgt8si1dWWEiJcF9xnM5DhX29IwYwPrXmfWU=; b=2wr/sKsCS0CJhEt46pvJVv7wNPWNUDIhiS0HsrZKOU6b6iFIPD28RUgCKuPrzRNAbV f5c+8Su+9WLC2EwJdVW3YOCuzy1lWMGqVEVPfd0Xzl1ezNTYPvicJXvbaVlP0zAPYwLb cxbGPc8o65kZBiwdkknA5jJQGYn6Iev1Iyt81pMe8E4PYJ+E8yC4r0+FgTHG8/r9NDyg Tilqu4huCp/VzAPTjx4EH+RCLgP193VqLqa5mjPgpY0no1Vr5HbI2Fnm/6vgTIKXNe3i aQaX4V8IebKh6dLLex+vt6sxijiQ0UzpbFFwTvZ2EfFYtqQRS3nfA7GyCbhtlPj7LN/n XzlA== X-Gm-Message-State: ACgBeo0Rarp0TfIIOFlyP1VSLFhhBAB7HkEe0+du8tDyqyWUFPV91cxb 3aSPY3y5WaT2bRrPDavLUqixMvqcw8LezNRl X-Google-Smtp-Source: AA6agR5273IB9tgSNHCOqAki+Ipeya7hsjlY8rd1GhIWf4OMAZR5Y3mjeMHG8FjOdpAg+raSOS25uQ== X-Received: by 2002:a05:6000:16ce:b0:228:62e0:37a6 with SMTP id h14-20020a05600016ce00b0022862e037a6mr7342748wrf.563.1662460803685; Tue, 06 Sep 2022 03:40:03 -0700 (PDT) Received: from helsinki-03.engr ([2a01:4f9:6b:2a47::2]) by smtp.gmail.com with ESMTPSA id z11-20020a056000110b00b00228dcf471e8sm327480wrw.56.2022.09.06.03.40.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 03:40:03 -0700 (PDT) From: mtsamis To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Kito Cheng , Christoph Muellner , Philipp Tomsich , mtsamis Subject: [PATCH] Enable shrink wrapping for the RISC-V target. Date: Tue, 6 Sep 2022 12:39:02 +0200 Message-Id: <20220906103902.2719585-1-manolis.tsamis@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This commit implements the target macros (TARGET_SHRINK_WRAP_*) that enable separate shrink wrapping for function prologues/epilogues in RISC-V. Tested against SPEC CPU 2017, this change always has a net-positive effect on the dynamic instruction count. See the following table for the breakdown on how this reduces the number of dynamic instructions per workload on a like-for-like (i.e., same config file; suppressing shrink-wrapping with -fno-shrink-wrap): # dynamic instructions w/o shrink-wrap w/ shrink-wrap reduction 500.perlbench_r 1265716786593 1262156218578 3560568015 0.28% 500.perlbench_r 779224795689 765337009025 13887786664 1.78% 500.perlbench_r 724087331471 711307152522 12780178949 1.77% 502.gcc_r 204259864844 194517006339 9742858505 4.77% 502.gcc_r 244047794302 231555834722 12491959580 5.12% 502.gcc_r 230896069400 221877703011 9018366389 3.91% 502.gcc_r 192130616624 183856450605 8274166019 4.31% 502.gcc_r 258875074079 247756203226 11118870853 4.30% 505.mcf_r 662653430325 660678680547 1974749778 0.30% 520.omnetpp_r 985114167068 934191310154 50922856914 5.17% 523.xalancbmk_r 927037633578 921688937650 5348695928 0.58% 525.x264_r 490953958454 490565583447 388375007 0.08% 525.x264_r 1994662294421 1993171932425 1490361996 0.07% 525.x264_r 1897617120450 1896062750609 1554369841 0.08% 531.deepsjeng_r 1695189878907 1669304130411 25885748496 1.53% 541.leela_r 1925941222222 1897900861198 28040361024 1.46% 548.exchange2_r 2073816227944 2073816226729 1215 0.00% 557.xz_r 379572090003 379057409041 514680962 0.14% 557.xz_r 953117469352 952680431430 437037922 0.05% 557.xz_r 536859579650 536456690164 402889486 0.08% 18421773405376 18223938521833 197834883543 1.07% totals Signed-off-by: Manolis Tsamis gcc/ChangeLog: * config/riscv/riscv.cc (struct machine_function): Add array to store register wrapping information. (riscv_for_each_saved_reg): Skip registers that are wrapped separetely. (riscv_get_separate_components): New function. (riscv_components_for_bb): Likewise. (riscv_disqualify_components): Likewise. (riscv_process_components): Likewise. (riscv_emit_prologue_components): Likewise. (riscv_emit_epilogue_components): Likewise. (riscv_set_handled_components): Likewise. (TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define. (TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise. (TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise. (TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/shrink-wrap-1.c: New test. --- gcc/config/riscv/riscv.cc | 187 +++++++++++++++++- .../gcc.target/riscv/shrink-wrap-1.c | 25 +++ 2 files changed, 210 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5a0adffb5ce..3b633149a9a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see #include "config.h" #include "system.h" #include "coretypes.h" +#include "backend.h" #include "tm.h" #include "rtl.h" #include "regs.h" @@ -52,6 +53,7 @@ along with GCC; see the file COPYING3. If not see #include "optabs.h" #include "bitmap.h" #include "df.h" +#include "function-abi.h" #include "diagnostic.h" #include "builtins.h" #include "predict.h" @@ -147,6 +149,11 @@ struct GTY(()) machine_function { /* The current frame information, calculated by riscv_compute_frame_info. */ struct riscv_frame_info frame; + + /* The components already handled by separate shrink-wrapping, which should + not be considered by the prologue and epilogue. */ + bool reg_is_wrapped_separately[FIRST_PSEUDO_REGISTER]; + }; /* Information about a single argument. */ @@ -4209,7 +4216,7 @@ riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn, for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) { - bool handle_reg = TRUE; + bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno]; /* If this is a normal return in a function that calls the eh_return builtin, then do not restore the eh return data registers as that @@ -4240,9 +4247,11 @@ riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn, for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) { + bool handle_reg = !cfun->machine->reg_is_wrapped_separately[regno]; machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; - riscv_save_restore_reg (mode, regno, offset, fn); + if (handle_reg) + riscv_save_restore_reg (mode, regno, offset, fn); offset -= GET_MODE_SIZE (mode); } } @@ -4667,6 +4676,156 @@ riscv_epilogue_uses (unsigned int regno) return false; } +/* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */ + +static sbitmap +riscv_get_separate_components (void) +{ + HOST_WIDE_INT offset; + sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER); + bitmap_clear (components); + + if (riscv_use_save_libcall (&cfun->machine->frame) + || cfun->machine->interrupt_handler_p) + return components; + + offset = cfun->machine->frame.gp_sp_offset; + for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) + { + if (SMALL_OPERAND (offset)) + bitmap_set_bit (components, regno); + + offset -= UNITS_PER_WORD; + } + + offset = cfun->machine->frame.fp_sp_offset; + for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) + { + machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; + + if (SMALL_OPERAND (offset)) + bitmap_set_bit (components, regno); + + offset -= GET_MODE_SIZE (mode); + } + + /* Don't mess with the hard frame pointer. */ + if (frame_pointer_needed) + bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM); + + bitmap_clear_bit (components, RETURN_ADDR_REGNUM); + + return components; +} + +/* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */ + +static sbitmap +riscv_components_for_bb (basic_block bb) +{ + bitmap in = DF_LIVE_IN (bb); + bitmap gen = &DF_LIVE_BB_INFO (bb)->gen; + bitmap kill = &DF_LIVE_BB_INFO (bb)->kill; + + sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER); + bitmap_clear (components); + + function_abi_aggregator callee_abis; + rtx_insn *insn; + FOR_BB_INSNS (bb, insn) + if (CALL_P (insn)) + callee_abis.note_callee_abi (insn_callee_abi (insn)); + HARD_REG_SET extra_caller_saves = callee_abis.caller_save_regs (*crtl->abi); + + /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */ + for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + if (!fixed_regs[regno] + && !crtl->abi->clobbers_full_reg_p (regno) + && (TEST_HARD_REG_BIT (extra_caller_saves, regno) + || bitmap_bit_p (in, regno) + || bitmap_bit_p (gen, regno) + || bitmap_bit_p (kill, regno))) + bitmap_set_bit (components, regno); + + for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) + if (!fixed_regs[regno] + && !crtl->abi->clobbers_full_reg_p (regno) + && (TEST_HARD_REG_BIT (extra_caller_saves, regno) + || bitmap_bit_p (in, regno) + || bitmap_bit_p (gen, regno) + || bitmap_bit_p (kill, regno))) + bitmap_set_bit (components, regno); + + return components; +} + +/* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */ + +static void +riscv_disqualify_components (sbitmap, edge, sbitmap, bool) +{ + /* Nothing to do for riscv. */ +} + +static void +riscv_process_components (sbitmap components, bool prologue_p) +{ + HOST_WIDE_INT offset; + riscv_save_restore_fn fn = prologue_p? riscv_save_reg : riscv_restore_reg; + + offset = cfun->machine->frame.gp_sp_offset; + for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) + { + if (bitmap_bit_p (components, regno)) + riscv_save_restore_reg (word_mode, regno, offset, fn); + + offset -= UNITS_PER_WORD; + } + + offset = cfun->machine->frame.fp_sp_offset; + for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) + if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) + { + machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; + + if (bitmap_bit_p (components, regno)) + riscv_save_restore_reg (mode, regno, offset, fn); + + offset -= GET_MODE_SIZE (mode); + } +} + +/* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */ + +static void +riscv_emit_prologue_components (sbitmap components) +{ + riscv_process_components (components, true); +} + +/* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */ + +static void +riscv_emit_epilogue_components (sbitmap components) +{ + riscv_process_components (components, false); +} + +static void +riscv_set_handled_components (sbitmap components) +{ + for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + if (bitmap_bit_p (components, regno)) + cfun->machine->reg_is_wrapped_separately[regno] = true; + + for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) + if (bitmap_bit_p (components, regno)) + cfun->machine->reg_is_wrapped_separately[regno] = true; +} + /* Return nonzero if this function is known to have a null epilogue. This allows the optimizer to omit jumps to jumps if no stack was created. */ @@ -5713,6 +5872,30 @@ riscv_asan_shadow_offset (void) #undef TARGET_FUNCTION_ARG_BOUNDARY #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary +#undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS +#define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \ + riscv_get_separate_components + +#undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB +#define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \ + riscv_components_for_bb + +#undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS +#define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \ + riscv_disqualify_components + +#undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS +#define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \ + riscv_emit_prologue_components + +#undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS +#define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \ + riscv_emit_epilogue_components + +#undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS +#define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \ + riscv_set_handled_components + /* The generic ELF target does not always have TLS support. */ #ifdef HAVE_AS_TLS #undef TARGET_HAVE_TLS diff --git a/gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c b/gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c new file mode 100644 index 00000000000..b05745968e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shrink-wrap-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-fshrink-wrap" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz" } } */ + +void g(void); + +void f(int x) +{ + if (x) + { + // Those only need to be saved if x is non-zero; without + // separate shrink-wrapping it would however be saved in all cases. + // Force saving of callee-saved registers + register int s2 asm("18") = x; + register int s3 asm("19") = x; + register int s4 asm("20") = x; + asm("" : : "r"(s2)); + asm("" : : "r"(s3)); + asm("" : : "r"(s4)); + g(); + } +} + +// The resulting code should do nothing if x == 0 +/* { dg-final { scan-assembler "bne\ta0,zero,.*\n.*ret" } } */ -- 2.34.1