From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 7CCCB3858D28 for ; Thu, 8 Sep 2022 01:51:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7CCCB3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowACnCA6JShljNpsEAA--.974S2; Thu, 08 Sep 2022 09:51:07 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, christoph.muellner@vrull.eu, jim.wilson.gcc@gmail.com, wuwei2016@iscas.ac.cn, Jiawei Subject: [PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc. Date: Thu, 8 Sep 2022 09:50:49 +0800 Message-Id: <20220908015049.2506-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:qwCowACnCA6JShljNpsEAA--.974S2 X-Coremail-Antispam: 1UD129KBjvJXoWxCr48uFWDtw4xZw1kuFWkXrb_yoW5Xry8pa 1DGr4Svr95AFZ29rsrtF4fWFy5twnagr45tr18Ar1UCw4kZrWjyFn3Kw4xZrnrXan8A34x ZF1j9a4Sk34UC37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkj14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV W8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xf McIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7 v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI 7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxV Cjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY 6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6x AIw20EY4v20xvaj40_WFyUJVCq3wCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv 6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUdHUDUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgMDAGKY1rAEjAAAse X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Jiawei Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option, it will add csr-check in .option section and pass this to assembler. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_file_start): New .option. * config/riscv/riscv.opt: New options. * doc/invoke.texi: New definations. --- gcc/config/riscv/riscv.cc | 5 +++++ gcc/config/riscv/riscv.opt | 6 ++++++ gcc/doc/invoke.texi | 6 ++++++ 3 files changed, 17 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 675d92c0961..e98e6b1f561 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5135,6 +5135,11 @@ riscv_file_start (void) if (! riscv_mrelax) fprintf (asm_out_file, "\t.option norelax\n"); + /* If the user specifies "-mcsr-check" on the command line then enable csr + check in the assembler. */ + if (riscv_mcsr_check) + fprintf (asm_out_file, "\t.option csr-check\n"); + if (riscv_emit_attribute_p) riscv_emit_attribute (); } diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index fbca91b956c..3a12dd47310 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1) Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. +mcsr-check +Target Bool Var(riscv_mcsr_check) Init(1) +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. + Mask(64BIT) Mask(MUL) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index dd3302fcd15..7caade26b94 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options. -mbig-endian -mlittle-endian @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg} @gol -mstack-protector-guard-offset=@var{offset}} +-mcsr-check -mno-csr-check @gol @emph{RL78 Options} @gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol @@ -28551,6 +28552,11 @@ linker relaxations. Emit (do not emit) RISC-V attribute to record extra information into ELF objects. This feature requires at least binutils 2.32. +@item -mcsr-check +@itemx -mno-csr-check +@opindex mcsr-check +Enables or disables the CSR checking. + @item -malign-data=@var{type} @opindex malign-data Control how GCC aligns variables and constants of array, structure, or union -- 2.34.1