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Fri, 9 Sep 2022 09:33:20 +0000 From: Christophe Lyon To: CC: Christophe Lyon Subject: [PATCH][GCC 12] arm: Fix constant immediates predicates and constraints for some MVE builtins Date: Fri, 9 Sep 2022 09:33:06 +0000 Message-ID: <20220909093306.2548388-1-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: VE1EUR03FT064:EE_|DBBPR08MB6042:EE_|DBAEUR03FT033:EE_|GV1PR08MB8450:EE_ X-MS-Office365-Filtering-Correlation-Id: cde74f21-b0fc-44e1-59c3-08da92465c6c x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: c971rulk28V9ztddtUJEk7EmQLYCR5i1iwLQdE/VKh7QoBZydcPAOo71s29wOc0V4+lGcMDhJcyFPyH9QnBhvvyGACR7Q37f9Fx1ApmUr9vJ+Rv0petEjXGHIYzEOFKXuGG3/MfeG23h8A/RAL7I0TkoirkMBdOA4TwWj1AHXqr1nJQ0Rve6UDZWsKS0ck4KN3juoeCdSLUurQF7TFcFjL0E4Z1LhH47Agca+atcxOVTmSwU1+mLCH/MXRonPgX86g/7Mn+IwmgnwrIhad5EQKt4ZItZZEPJ1GlP1Dkm5U0d85m2Popo7ZgOK+1Bh0VRABP+AD7oK776eRAlcN05sm/FJNXwc7SITd67jLzJFI5ar/2EJ6lteF72MozIS8IGQm+SMh2t6u8xGe8Oc54vO8055qhBqFWUMwMAmF8YqqEH/W83TxTigalBY0+YKxIzhwjxeingEmqyCTA4/RMrWQxyGRJ0RA1dnwH2Ii9sXeV0oxrslhiwP/PKAvsPekJC7tftX8znudu8I0Kyo4rVJIrsLweXKhDSkknFQ0ayqpMiP0ci9LGaZ5/roPnQkEfFzbLH0ztg4HIoDn/21NuVnCg9/OiLVOE2eBmF0Qm0hGeBH9sEOWXdrs4F8srJEqpj+2IrZmFZz/UCZLMbFtusqtpP3O8WsGmagaxXIGh8+s1lfCCe9+wGIkJJ/UVtMCJ3q3kQ8qovanTQWT2+S3ab09cvxKgHhO4zPwgziRhods2pkHX//ZNuDa2IQfBweDFZGRMZu5NqNWf2wLUSL7/bJmnw/dWAhIeoNrlFgwJlhIIOjRooCKvPEyUBMYqDjGFyxGpZIu9RTa8yH41Ea+brig== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(396003)(346002)(376002)(39860400002)(136003)(46966006)(36840700001)(40470700004)(44832011)(8936002)(2906002)(5660300002)(82310400005)(40480700001)(40460700003)(86362001)(81166007)(356005)(36756003)(7696005)(36860700001)(6666004)(26005)(478600001)(47076005)(41300700001)(2616005)(336012)(83380400001)(426003)(1076003)(186003)(82740400003)(316002)(6916009)(70586007)(70206006)(8676002)(4326008)(14773001)(36900700001);DIR:OUT;SFP:1101; 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Several MVE builtins incorrectly use the same predicate/constraint pair for several modes, which does not match the specification. This patch uses the appropriate iterator instead. 2022-09-06 Christophe Lyon gcc/ * config/arm/mve.md (mve_vqshluq_n_s): Use MVE_pred/MVE_constraint instead of mve_imm_7/Ra. (mve_vqshluq_m_n_s): Likewise. (mve_vqrshrnbq_n_): Use MVE_pred3/MVE_constraint3 instead of mve_imm_8/Rb. (mve_vqrshrunbq_n_s): Likewise. (mve_vqrshrntq_n_): Likewise. (mve_vqrshruntq_n_s): Likewise. (mve_vrshrnbq_n_): Likewise. (mve_vrshrntq_n_): Likewise. (mve_vqrshrnbq_m_n_): Likewise. (mve_vqrshrntq_m_n_): Likewise. (mve_vrshrnbq_m_n_): Likewise. (mve_vrshrntq_m_n_): Likewise. (mve_vqrshrunbq_m_n_s): Likewise. (mve_vsriq_n_): Likewise. (cheerry-picked from c3fb6658c7670e446f2fd00984404d971e416b3c) --- gcc/config/arm/mve.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index f16991c0a34..469e7e7f8dc 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1617,7 +1617,7 @@ (define_insn "mve_vqshluq_n_s" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w") - (match_operand:SI 2 "mve_imm_7" "Ra")] + (match_operand:SI 2 "" "")] VQSHLUQ_N_S)) ] "TARGET_HAVE_MVE" @@ -2608,7 +2608,7 @@ (define_insn "mve_vqrshrnbq_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -2623,7 +2623,7 @@ (define_insn "mve_vqrshrunbq_n_s" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRUNBQ_N_S)) ] "TARGET_HAVE_MVE" @@ -3563,7 +3563,7 @@ (define_insn "mve_vsriq_n_" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg")] + (match_operand:SI 3 "" "")] VSRIQ_N)) ] "TARGET_HAVE_MVE" @@ -4466,7 +4466,7 @@ (define_insn "mve_vqrshrntq_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4482,7 +4482,7 @@ (define_insn "mve_vqrshruntq_n_s" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VQRSHRUNTQ_N_S)) ] "TARGET_HAVE_MVE" @@ -4770,7 +4770,7 @@ (define_insn "mve_vrshrnbq_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VRSHRNBQ_N)) ] "TARGET_HAVE_MVE" @@ -4786,7 +4786,7 @@ (define_insn "mve_vrshrntq_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb")] + (match_operand:SI 3 "" "")] VRSHRNTQ_N)) ] "TARGET_HAVE_MVE" @@ -4980,7 +4980,7 @@ (define_insn "mve_vqshluq_m_n_s" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_7" "Ra") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQSHLUQ_M_N_S)) ] @@ -5012,7 +5012,7 @@ (define_insn "mve_vsriq_m_n_" (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") (match_operand:MVE_2 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VSRIQ_M_N)) ] @@ -6131,7 +6131,7 @@ (define_insn "mve_vqrshrnbq_m_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRNBQ_M_N)) ] @@ -6148,7 +6148,7 @@ (define_insn "mve_vqrshrntq_m_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRNTQ_M_N)) ] @@ -6216,7 +6216,7 @@ (define_insn "mve_vrshrnbq_m_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VRSHRNBQ_M_N)) ] @@ -6233,7 +6233,7 @@ (define_insn "mve_vrshrntq_m_n_" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VRSHRNTQ_M_N)) ] @@ -6454,7 +6454,7 @@ (define_insn "mve_vqrshrunbq_m_n_s" (set (match_operand: 0 "s_register_operand" "=w") (unspec: [(match_operand: 1 "s_register_operand" "0") (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "mve_imm_8" "Rb") + (match_operand:SI 3 "" "") (match_operand: 4 "vpr_register_operand" "Up")] VQRSHRUNBQ_M_N_S)) ] -- 2.34.1