From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id E5FE63858C74 for ; Thu, 15 Sep 2022 06:54:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E5FE63858C74 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28EM6gBb009317; Thu, 15 Sep 2022 08:54:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type : content-transfer-encoding; s=selector1; bh=8TtwSjcmUiQrDyDrtA6t9S+tKf0Q/qy7q/h386YDgJY=; b=zt9MqFQSWLg+kNFBctHwu3u60yAunycjyGpEantwOKjM3jBDOx7Po3c0zC9+IICQkP6i x/NJdFS8DfODRt97SHDRK2zfz8Sq3oHeDovfnCQ7kWldRT/43IXI62vursogFgW+OHzN EuFMzuA1GwzT6hZnQrHDkJ0FCE1MpXP61Q5PaRTBZsERbRd5E9kw0p61nv20LqZDlFSf Zv9GblEd8IgRK5kuWGw4V9P6x50hNp0nhLPGHjPEbktu1MVrHS/w4e4/7f13z4Eop6XZ PN12LpDgkovu9Wmc0Kg/B+CfGwhM44xnFDHFRdYzN7YcOat2egref1WHzlxrB9GQxbTj HQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jjxxatp21-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Sep 2022 08:54:37 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CB26B10002A; Thu, 15 Sep 2022 08:54:35 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9FACA214D0F; Thu, 15 Sep 2022 08:54:35 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Thu, 15 Sep 2022 08:54:32 +0200 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , , , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Subject: [PATCH] testsuite: Disable zero-scratch-regs-{7, 9, 11}.c on arm Date: Thu, 15 Sep 2022 08:54:16 +0200 Message-ID: <20220915065416.1172508-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.120] X-ClientProxiedBy: GPXDAG2NODE4.st.com (10.75.127.68) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-15_03,2022-09-14_04,2022-06-22_01 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: -fzero-call-used-regs=all and -fzero-call-used-regs=all-gpr are not supported on arm*. On arm-none-eabi, the testcases fails with: sorry, unimplemented: '-fzero-call-used-regs' not supported on this target 2022-09-15 Torbjörn SVENSSON gcc/testsuite/ChangeLog: * c-c++-common/zero-scratch-regs-7.c: Skip on arm. * c-c++-common/zero-scratch-regs-9.c: Likewise. * c-c++-common/zero-scratch-regs-11.c: Likewise. Co-Authored-By: Yvan ROUX Signed-off-by: Torbjörn SVENSSON --- gcc/testsuite/c-c++-common/zero-scratch-regs-11.c | 2 +- gcc/testsuite/c-c++-common/zero-scratch-regs-7.c | 1 + gcc/testsuite/c-c++-common/zero-scratch-regs-9.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c index b7739b2c6f6..6fd2a1dc382 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-10.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-7.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-7.c index 2a4c8b2e73d..c684b4a02f9 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-7.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-7.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-skip-if "not implemented" { ia64*-*-* } } */ +/* { dg-skip-if "not implemented" { arm*-*-* } } */ /* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */ #include "zero-scratch-regs-1.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c index ea83bc146b7..0e8922053e8 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-1.c" -- 2.25.1