From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id B465C3858D38 for ; Thu, 22 Sep 2022 16:41:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B465C3858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28MDkv42011597; Thu, 22 Sep 2022 18:41:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type : content-transfer-encoding; s=selector1; bh=BHnjOyvs49wM4pVw5D174plS732Ien+STWjW0XxyQWM=; b=c8H0A+5DQ3mDyoxSAFXjMJSO3UQh43TOj5AgJ3g9eoGFx8zdtBqUAMKk6ML4AsB05Cij bFHDBn31E4YLrm6NnO+fzTwctaWGOFjzE9ByrZbodrwaN5Dh/wy9/LPtWJguGEZqnJrC t+PZ8llec7dEqFWzXUc+QMtwTT9ZsVBv3SW8lyhvHBS8rppm66FZRN2wgf5l1oXYHiFi hiKTZ0XD/nuSudZGipzqdUenc9ksT//F6eGeCA+ze4yRacybHlC1WiRW0r7NCA3YqePD E/YquJO3udPBrcw/3lghbuagg6hzdiC3YJ5mRrXnVrpcThu1MkpyVOQ7A/qNQUVjICIb MQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jn6g5sa74-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Sep 2022 18:41:20 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9D6D710002A; Thu, 22 Sep 2022 18:41:18 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8ADAF26DDB6; Thu, 22 Sep 2022 18:41:18 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.49) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Thu, 22 Sep 2022 18:41:18 +0200 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , , , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Subject: [PATCH] testsuite: Sanitize fails for SP FPU on Arm Date: Thu, 22 Sep 2022 18:40:58 +0200 Message-ID: <20220922164057.4107373-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.49] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-22_11,2022-09-22_01,2022-06-22_01 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch stops reporting fails for Arm targets with single precision floating point unit for types wider than 32 bits (the width of float on arm-none-eabi). As reported in PR102017, fenv is reported as supported in recent versions of newlib. At the same time, for some Arm targets, the implementation in libgcc does not support exceptions and thus, the test fails with a call to abort(). gcc/testsuite/ChangeLog: * gcc.dg/c2x-float-7.c: Invert the exception check for Arm targets with SP FPU. * gcc.dg/pr95115.c: Likewise. * gcc.dg/torture/float32x-nan-floath.c: Likewise. * gcc.dg/torture/float32x-nan.c: Likewise. * gcc.dg/torture/float64-nan-floath.c: Likewise. * gcc.dg/torture/float64-nan.c: Likewise. * gcc.dg/torture/inf-compare-1.c: Likewise. * gcc.dg/torture/inf-compare-2.c: Likewise. * gcc.dg/torture/inf-compare-3.c: Likewise. * gcc.dg/torture/inf-compare-4.c: Likewise. Co-Authored-By: Yvan ROUX Signed-off-by: Torbjörn SVENSSON --- gcc/testsuite/gcc.dg/c2x-float-7.c | 10 ++++++++++ gcc/testsuite/gcc.dg/pr95115.c | 5 +++++ gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h | 5 +++++ gcc/testsuite/gcc.dg/torture/floatn-nan.h | 10 ++++++++++ gcc/testsuite/gcc.dg/torture/inf-compare-1.c | 5 +++++ gcc/testsuite/gcc.dg/torture/inf-compare-2.c | 5 +++++ gcc/testsuite/gcc.dg/torture/inf-compare-3.c | 5 +++++ gcc/testsuite/gcc.dg/torture/inf-compare-4.c | 5 +++++ 8 files changed, 50 insertions(+) diff --git a/gcc/testsuite/gcc.dg/c2x-float-7.c b/gcc/testsuite/gcc.dg/c2x-float-7.c index 0c90ff24165..c699e94aff8 100644 --- a/gcc/testsuite/gcc.dg/c2x-float-7.c +++ b/gcc/testsuite/gcc.dg/c2x-float-7.c @@ -39,11 +39,21 @@ main (void) abort (); feclearexcept (FE_ALL_EXCEPT); d += d; +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (fetestexcept (FE_INVALID)) +#else if (!fetestexcept (FE_INVALID)) +#endif abort (); feclearexcept (FE_ALL_EXCEPT); ld += ld; +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (fetestexcept (FE_INVALID)) +#else if (!fetestexcept (FE_INVALID)) +#endif abort (); exit (0); } diff --git a/gcc/testsuite/gcc.dg/pr95115.c b/gcc/testsuite/gcc.dg/pr95115.c index 46a95dfb698..15bc6854819 100644 --- a/gcc/testsuite/gcc.dg/pr95115.c +++ b/gcc/testsuite/gcc.dg/pr95115.c @@ -19,7 +19,12 @@ main (void) double r = x (); if (!__builtin_isnan (r)) abort (); +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (fetestexcept (FE_INVALID)) +#else if (!fetestexcept (FE_INVALID)) +#endif abort (); exit (0); } diff --git a/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h b/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h index 9892fd0cf63..5c9f28d4fdc 100644 --- a/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h +++ b/gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h @@ -30,7 +30,12 @@ main (void) { volatile TYPE r; r = nans_cst + nans_cst; +#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32) + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (fetestexcept (FE_INVALID)) +#else if (!fetestexcept (FE_INVALID)) +#endif abort (); exit (0); } diff --git a/gcc/testsuite/gcc.dg/torture/floatn-nan.h b/gcc/testsuite/gcc.dg/torture/floatn-nan.h index 89d2e2eec34..0abb0668677 100644 --- a/gcc/testsuite/gcc.dg/torture/floatn-nan.h +++ b/gcc/testsuite/gcc.dg/torture/floatn-nan.h @@ -30,10 +30,20 @@ main (void) { volatile TYPE r; r = nan_cst + nan_cst; +#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32) + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (!fetestexcept (FE_INVALID)) +#else if (fetestexcept (FE_INVALID)) +#endif abort (); r = nans_cst + nans_cst; +#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32) + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (fetestexcept (FE_INVALID)) +#else if (!fetestexcept (FE_INVALID)) +#endif abort (); exit (0); } diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-1.c b/gcc/testsuite/gcc.dg/torture/inf-compare-1.c index 70f255e680a..df0e61d9f89 100644 --- a/gcc/testsuite/gcc.dg/torture/inf-compare-1.c +++ b/gcc/testsuite/gcc.dg/torture/inf-compare-1.c @@ -16,6 +16,11 @@ int main (void) { i = x > __builtin_inf (); +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (i != 0 || fetestexcept (FE_INVALID)) +#else if (i != 0 || !fetestexcept (FE_INVALID)) +#endif abort (); } diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-2.c b/gcc/testsuite/gcc.dg/torture/inf-compare-2.c index 011f992d5a0..dcb43ccc444 100644 --- a/gcc/testsuite/gcc.dg/torture/inf-compare-2.c +++ b/gcc/testsuite/gcc.dg/torture/inf-compare-2.c @@ -16,6 +16,11 @@ int main (void) { i = x < -__builtin_inf (); +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (i != 0 || fetestexcept (FE_INVALID)) +#else if (i != 0 || !fetestexcept (FE_INVALID)) +#endif abort (); } diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-3.c b/gcc/testsuite/gcc.dg/torture/inf-compare-3.c index de5c478a8d8..1cd4d3e8199 100644 --- a/gcc/testsuite/gcc.dg/torture/inf-compare-3.c +++ b/gcc/testsuite/gcc.dg/torture/inf-compare-3.c @@ -16,6 +16,11 @@ int main (void) { i = x <= __builtin_inf (); +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (i != 0 || fetestexcept (FE_INVALID)) +#else if (i != 0 || !fetestexcept (FE_INVALID)) +#endif abort (); } diff --git a/gcc/testsuite/gcc.dg/torture/inf-compare-4.c b/gcc/testsuite/gcc.dg/torture/inf-compare-4.c index 685562d3a40..0cd27076079 100644 --- a/gcc/testsuite/gcc.dg/torture/inf-compare-4.c +++ b/gcc/testsuite/gcc.dg/torture/inf-compare-4.c @@ -16,6 +16,11 @@ int main (void) { i = x >= -__builtin_inf (); +#if defined(__ARM_FP) && __ARM_FP == 4 + /* Arm with SP FPU does not support exceptions (see pr102017). */ + if (i != 0 || fetestexcept (FE_INVALID)) +#else if (i != 0 || !fetestexcept (FE_INVALID)) +#endif abort (); } -- 2.25.1