From: "Torbjörn SVENSSON" <torbjorn.svensson@foss.st.com>
To: <gcc-patches@gcc.gnu.org>
Cc: "Torbjörn SVENSSON" <torbjorn.svensson@foss.st.com>
Subject: [PATCH] Fix typo in chapter level for RISC-V attributes
Date: Fri, 23 Sep 2022 20:43:44 +0200 [thread overview]
Message-ID: <20220923184344.4147951-1-torbjorn.svensson@foss.st.com> (raw)
The "RISC-V specific attributes" section should be at the same level
as "PowerPC-specific attributes".
gcc/ChangeLog:
* doc/sourcebuild.texi: Fix chapter level.
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
---
gcc/doc/sourcebuild.texi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 760ff9559a6..52357cc7aee 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2447,7 +2447,7 @@ PowerPC target pre-defines macro _ARCH_PWR9 which means the @code{-mcpu}
setting is Power9 or later.
@end table
-@subsection RISC-V specific attributes
+@subsubsection RISC-V specific attributes
@table @code
--
2.25.1
next reply other threads:[~2022-09-23 18:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 18:43 Torbjörn SVENSSON [this message]
2022-09-24 18:34 ` Jeff Law
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