From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 74C363857B9D for ; Sun, 25 Sep 2022 11:25:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 74C363857B9D Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1664105151; bh=fET6j4lbQ3rmOxEo1l9i2cgB+l195pCM2H9Xw5akb7I=; h=From:To:Cc:Subject:Date:From; b=lJmi/yZTiDzjCWB/2D+tlYZblSk4OhAsHtGyEXPTgSUu8zdKsNBnWVjOGMHfdjvMA FQrTrfJIR0pSy5p81RLCDz81gMNLB9ACbczRe6HgtTa0Sv4plP8he0iVI1Bj5yQKHS aEQID+iw3PWc14D740+5ALOjISKQ9HyuXZcdnR8w= Received: from xry111-x57s1.. (unknown [IPv6:240e:358:1175:c300:dc73:854d:832e:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 31C4D6683D; Sun, 25 Sep 2022 07:25:46 -0400 (EDT) From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Wang Xuerui , Chenghua Xu , Xi Ruoyao Subject: [PATCH] LoongArch: Add prefetch instruction Date: Sun, 25 Sep 2022 19:25:37 +0800 Message-Id: <20220925112537.2209847-1-xry111@xry111.site> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FROM_SUSPICIOUS_NTLD,FROM_SUSPICIOUS_NTLD_FP,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_PDS_OTHER_BAD_TLD autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The test pr106397.c fails on LoongArch because we don't have defined prefetch instruction. We can silence the test for LoongArch, but it's not too difficult to add the prefetch instruction so add it now. -- >8 -- gcc/ChangeLog: * config/loongarch/constraints.md (ZD): New address constraint. * config/loongarch/loongarch.md (prefetch): New insn. --- gcc/config/loongarch/constraints.md | 6 ++++++ gcc/config/loongarch/loongarch.md | 14 ++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md index 43cb7b5f0f5..93da5970958 100644 --- a/gcc/config/loongarch/constraints.md +++ b/gcc/config/loongarch/constraints.md @@ -190,3 +190,9 @@ (define_memory_constraint "ZB" The offset is zero" (and (match_code "mem") (match_test "REG_P (XEXP (op, 0))"))) + +(define_address_constraint "ZD" + "An address operand whose address is formed by a base register and offset + that is suitable for use in instructions with the same addressing mode + as @code{preld}." + (match_test "loongarch_12bit_offset_address_p (op, mode)")) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 214b14bddd3..84c1bd1c0d6 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -2137,6 +2137,20 @@ (define_insn "loongarch_dbar" "" "dbar\t%0") +(define_insn "prefetch" + [(prefetch (match_operand 0 "address_operand" "ZD") + (match_operand 1 "const_uimm5_operand" "i") + (match_operand 2 "const_int_operand" "n"))] + "" +{ + switch (INTVAL (operands[1])) + { + case 0: return "preld\t0,%a0"; + case 1: return "preld\t8,%a0"; + default: gcc_unreachable (); + } +}) + ;; Privileged state instruction -- 2.37.0