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From: Philipp Tomsich <>
Cc: Tamar Christina <>,
	Christoph Muellner <>,
	Richard Sandiford <>,
	Philipp Tomsich <>
Subject: [PATCH] aarch64: update Ampere-1 core definition
Date: Mon,  3 Oct 2022 23:24:02 +0200	[thread overview]
Message-ID: <> (raw)

This brings the extensions detected by -mcpu=native on Ampere-1 systems
in sync with the defaults generated for -mcpu=ampere1.

Note that some kernel versions may misreport the presence of PAUTH and
PREDRES (i.e., -mcpu=native will add 'nopauth' and 'nopredres').


	* config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
          Ampere-1 core entry.

Signed-off-by: Philipp Tomsich <>

Ok for backport?

 gcc/config/aarch64/aarch64-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 60299160bb6..9090f80b4b7 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -69,7 +69,7 @@ AARCH64_CORE("thunderxt81",   thunderxt81,   thunderx,  V8A,  (CRC, CRYPTO), thu
 AARCH64_CORE("thunderxt83",   thunderxt83,   thunderx,  V8A,  (CRC, CRYPTO), thunderx,  0x43, 0x0a3, -1)
 /* Ampere Computing ('\xC0') cores. */
-AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (), ampere1, 0xC0, 0xac3, -1)
+AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RCPC, RNG, AES, SHA3), ampere1, 0xC0, 0xac3, -1)
 /* Do not swap around "emag" and "xgene1",
    this order is required to handle variant correctly. */
 AARCH64_CORE("emag",        emag,      xgene1,    V8A,  (CRC, CRYPTO), emag, 0x50, 0x000, 3)

             reply	other threads:[~2022-10-03 21:24 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03 21:24 Philipp Tomsich [this message]
2022-10-04 16:43 ` Richard Sandiford
2022-10-06  9:16   ` Philipp Tomsich

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