From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id E353D3858406 for ; Mon, 10 Oct 2022 07:29:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E353D3858406 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x630.google.com with SMTP id d26so15900764eje.10 for ; Mon, 10 Oct 2022 00:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vo1KNz4Er543qD+wXmKi/wibR8dK82ZgHdTcVrvLAqs=; b=m1iNeGPiqbBQQcs1r5NutJKA3wPbHNdvI0DFG1OEOuZ+aMBdEWbIH9BGXf8v30Td/j 7U5YUYNqFxNO2zxKnoqf8P1Kfi0Z4jblnDtEIuElwpiOrk1eHZqqTYseHNusCtv2ZMx0 /Wth8tbovUFdQLDcELN2Un63semNQV7vdl7Ww8sHtckB3pVzE8vgYfje1ZGkK2ggT3eu TBDP/O6ex6uDxNiBh2CcH0oY4MgvJENuLbGQ+rM3OZX56EO6Fq9Rbr2XjNFZnVtYhQh9 o4HD7TLlAzeDb4DdRnE8MKpItGkrsPr+1di6OY9FgII1EHgfwwVQsPqXYRiFeOrS16Rp SpdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vo1KNz4Er543qD+wXmKi/wibR8dK82ZgHdTcVrvLAqs=; b=1PjZwHyJwwmv8/U8CdzyzyI1Wk2Bl2RubHudFZ8ETwPx2I7qcKjjRgaDrllXBJOZss /bCRam7zu29QVk16vPIRzb5pqMKEyhu+597rQxY5aAo/GhJL0C5YqiK0cK3muu6dMZ6/ 2XUSfYDvrLx/k/GfMekuKfWhU2KlXuXcAiRkS7G54hf5abF26D8bttIci0xx275ONwcj S4uvPT2XQfS3k2X64ZUucdhOE+m+B1ZPxO+ZoYnvPpzv/bWcjp7D+nsKjwun2uRuDWqv JOEw4IA64YL+nuQSF+Gf5wcY1EbeTd5RjDMYX5xUcfoQilp35aQyqXAebkehMvf9oTyT ieqw== X-Gm-Message-State: ACrzQf2hA9RHT/d5e74HYDrVR9cpyWm1pPkgNQddleGgYF2jRan8V0+U CQ1vRRc06+XKfahb/W/aRRoqHcix2mg= X-Google-Smtp-Source: AMsMyM5iqvXYH/6S9gOOcGYae2guvuSQzYzvrJ5+VVUqN/euWybnawIMV5yA4l8Cooidf4aKEl8m6g== X-Received: by 2002:a17:907:31c4:b0:78d:9b2f:4e1a with SMTP id xf4-20020a17090731c400b0078d9b2f4e1amr7497488ejb.306.1665386945327; Mon, 10 Oct 2022 00:29:05 -0700 (PDT) Received: from fatty.nomansland ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id j1-20020a17090623e100b007317f017e64sm4901913ejg.134.2022.10.10.00.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 00:29:04 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com Subject: [committed 2/5] arc: Remove Rcr constraint Date: Mon, 10 Oct 2022 10:28:59 +0300 Message-Id: <20221010072902.3669746-2-claziss@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221010072902.3669746-1-claziss@gmail.com> References: <20221010072902.3669746-1-claziss@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/arc/arc.md(mulsi3_700): Remove Rcr. (mulsi3_highpart): Likewise. (umulsi3_highpart_i): Likewise. (umulsi3_highpart_int): Likewise. (macd): Likewise. (macdu): Likewise. * config/arc/constraints.md (Rcr): Remove it. gcc/testsuite/ChangeLog: * gcc.target/arc/tmac-2.c: Update test. Signed-off-by: Claudiu Zissulescu fix --- gcc/config/arc/arc.md | 36 +++++++++++++-------------- gcc/config/arc/constraints.md | 10 -------- gcc/testsuite/gcc.target/arc/tmac-2.c | 2 +- 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 7170445309f..90ce66d45ba 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2336,11 +2336,11 @@ (define_insn "mulu64" ; registers, since it cannot be the destination of a multi-cycle insn ; like MPY or MPYU. (define_insn "mulsi3_700" - [(set (match_operand:SI 0 "mpy_dest_reg_operand" "=Rcr,r,r,Rcr,r") - (mult:SI (match_operand:SI 1 "register_operand" "%0,c,0,0,c") - (match_operand:SI 2 "nonmemory_operand" "cL,cL,I,Cal,Cal")))] + [(set (match_operand:SI 0 "mpy_dest_reg_operand" "=r, r,r, r,r") + (mult:SI (match_operand:SI 1 "register_operand" "%0, r,0, 0,r") + (match_operand:SI 2 "nonmemory_operand" "rL,rL,I,Cal,Cal")))] "TARGET_ARC700_MPY" - "mpyu%? %0,%1,%2" + "mpyu%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "type" "umulti") (set_attr "predicable" "yes,no,no,yes,no") @@ -2501,15 +2501,15 @@ (define_insn_and_split "mulsidi3_700" (set_attr "length" "8")]) (define_insn "mulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "=Rcr,r,Rcr,r") + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c, 0,c")) - (sign_extend:DI (match_operand:SI 2 "extend_operand" "c,c, i,i"))) + (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,0,r")) + (sign_extend:DI (match_operand:SI 2 "extend_operand" "r,r,i,i"))) (const_int 32))))] "TARGET_MPY" - "mpy%+%? %0,%1,%2" + "mpy%+%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,yes,no") @@ -2518,15 +2518,15 @@ (define_insn "mulsi3_highpart" ; Note that mpyhu has the same latency as mpy / mpyh, ; thus we use the type multi. (define_insn "*umulsi3_highpart_i" - [(set (match_operand:SI 0 "register_operand" "=Rcr,r,Rcr,r") + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") (truncate:SI (lshiftrt:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c, 0,c")) - (zero_extend:DI (match_operand:SI 2 "extend_operand" "c,c, i,i"))) + (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,0,r")) + (zero_extend:DI (match_operand:SI 2 "extend_operand" "r,r,i,i"))) (const_int 32))))] "TARGET_MPY" - "mpy%+u%? %0,%1,%2" + "mpy%+u%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,yes,no") @@ -2536,15 +2536,15 @@ (define_insn "*umulsi3_highpart_i" ;; need a separate pattern for immediates ;; ??? This is fine for combine, but not for reload. (define_insn "umulsi3_highpart_int" - [(set (match_operand:SI 0 "register_operand" "=Rcr, r, r,Rcr, r") + [(set (match_operand:SI 0 "register_operand" "=r, r, r,r, r") (truncate:SI (lshiftrt:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c, 0, 0, c")) - (match_operand:DI 2 "immediate_usidi_operand" "L, L, I, Cal, Cal")) + (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, r, 0, 0, r")) + (match_operand:DI 2 "immediate_usidi_operand" "L, L, I,Cal,Cal")) (const_int 32))))] "TARGET_MPY" - "mpy%+u%? %0,%1,%2" + "mpy%+u%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,no,yes,no") @@ -6141,7 +6141,7 @@ (define_insn_and_split "maddsidi4_split" (set_attr "length" "36")]) (define_insn "macd" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r") + [(set (match_operand:DI 0 "even_register_operand" "=r,r,r") (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) @@ -6243,7 +6243,7 @@ (define_insn_and_split "umaddsidi4_split" (set_attr "length" "36")]) (define_insn "macdu" - [(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r") + [(set (match_operand:DI 0 "even_register_operand" "=r,r,r") (plus:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r")) diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 02aa37ffeca..039954ef048 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -466,16 +466,6 @@ (define_constraint "Rcw" && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], REGNO (op))"))) -(define_constraint "Rcr" - "@internal - Cryptic r - for use in early alternatives with matching constraint" - (and (match_code "reg") - (match_test - "TARGET_Rcw - && REGNO (op) < FIRST_PSEUDO_REGISTER - && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], - REGNO (op))"))) - (define_constraint "Rcb" "@internal Stack Pointer register @code{r28} - do not reload into its class" diff --git a/gcc/testsuite/gcc.target/arc/tmac-2.c b/gcc/testsuite/gcc.target/arc/tmac-2.c index ee1339a2f23..2bd051bb24c 100644 --- a/gcc/testsuite/gcc.target/arc/tmac-2.c +++ b/gcc/testsuite/gcc.target/arc/tmac-2.c @@ -7,5 +7,5 @@ /* { dg-final { scan-assembler "mac " } } */ /* { dg-final { scan-assembler "macu" } } */ -/* { dg-final { scan-assembler "mpym " } } */ +/* { dg-final { scan-assembler "mpym\\t" } } */ /* { dg-final { scan-assembler "mpymu" } } */ -- 2.30.2