From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id 485CC38582A8 for ; Mon, 10 Oct 2022 07:29:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 485CC38582A8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x634.google.com with SMTP id b2so23038774eja.6 for ; Mon, 10 Oct 2022 00:29:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rsjn9AiyU261BdpEs71+oWWQ9sSBq0HLGXUomHSsnP4=; b=YDqnj1CHC0OhhBg4CIu25fIhYalEdr2UJ7+DVwWIhhShP0HHMcgHzjZkd7wf70dq0S u6dULOs72wzKlzVRK0YQHt8t6CCD/YZ10e+I/bew0TBLyul0O1vJQ65n26kp6vzaZ3p7 uJo/3ig0JEdNbX4X7ke079FIpeWDdZuQ37zf+eVkqe01I1p/emrqBcr+uYPJVwnRzQDV IsuTugwda7QtaK+auWiBJ1Xv7zzKGG2+xoDVHVBJSrg7JL/eflnaw4LO7KLAwiOUvFkZ AacP3gbBJP5dmS49BpLc7XhadXMwqTwLqpfLLnULb+dgEIu2qoi1GCUsNkrp6tXVwBab 9zmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rsjn9AiyU261BdpEs71+oWWQ9sSBq0HLGXUomHSsnP4=; b=l45lhQx9RgkTOkRSi/69VovsAvCXY7FiU45j81XuCHoJerj+ncm5oEknZboPz+k7BF jherCr2rsj4sBbasZz1jTM96FcPvS1YyPV/2G8LuB79r0Buwo6DDoMC9fGd3qTfVcist RfrFGt4E3QN5M3QYAXLrhPob2BFCQ1X8F7NhwvfKi4KtMFR/xPsIlY0QmwFzCOP8aCdC rkKUBbRLjMY4lrB/wIDxthqymOee3gc2ZV3ae4WcATH89kTQMXMsiSdU57SwL1MLJGpv I0TfLhEy6dxYxpyrzTUrTrBzVQ/nZaAGjSmQrme8Q/AoG1lDdDY5oLSwlQPAppvqXeGO t+rQ== X-Gm-Message-State: ACrzQf18bY73r6KfCCJvuwvwTKhvAbvyLZEw1tGg4xkKAHItU85tZbgL RrtGCRlDbJhE/+7dzfBeiilzzVPmoPc= X-Google-Smtp-Source: AMsMyM7dpJXup/cQB9pjXhc0j9O5B3PMZ+yWCybGUejG2AyF+bq+RzioiFBJiMmEKBC1FExcxIyRoQ== X-Received: by 2002:a17:906:ee89:b0:73d:70c5:1a4e with SMTP id wt9-20020a170906ee8900b0073d70c51a4emr13257963ejb.683.1665386946913; Mon, 10 Oct 2022 00:29:06 -0700 (PDT) Received: from fatty.nomansland ([193.187.151.25]) by smtp.gmail.com with ESMTPSA id j1-20020a17090623e100b007317f017e64sm4901913ejg.134.2022.10.10.00.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 00:29:06 -0700 (PDT) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: fbedard@synopsys.com Subject: [committed 4/5] arc: Remove Rcq constraint. Date: Mon, 10 Oct 2022 10:29:01 +0300 Message-Id: <20221010072902.3669746-4-claziss@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221010072902.3669746-1-claziss@gmail.com> References: <20221010072902.3669746-1-claziss@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ * config/arc/arc.cc (arc_check_short_reg_p): New function. (arc_address_cost): Replace satisfies_constraint_Rcq with the above new function. (arc_output_addsi): Likewise. (split_addsi): Likewise. (split_subsi): Likewise. * config/arc/arc.md (movqi_insn): Remove Rcq constraint. (movhi_insn): Likewise. (movsi_insn): Likewise. (tst_movb): Likewise. (tst): Likewise. (tst_bitfield): Likewise. (abssi2): Likewise. (addsi3_mixed): Likewise. (mulhisi3_reg): Likewise. (umulhisi3_reg): Likewise. (mulsi_600): Likewise. (mul64): Likewise. (subsi3_insn): Likewise. (bicsi3_insn): Likewise. (xorsi3): Likewise. (negsi2): Likewise. (one_cmplsi2): Likewise. (lshrsi3_insn): Likewise. (cmpsi_cc_insn_mixed): Likewise. (cmpsi_cc_zn_insn): Likewise. (btst): Likewise. (cmpsi_cc_z_insn): Likewise. (cmpsi_cc_c_insn): Likewise. (indirect_jump): Likewise. (casesi_jump): Likewise. (call_i): Likewise. (call_value_i): Likewise. (bbit): Likewise. (abssf2): Likewise. (ashlsi2_cnt1): Likewise. (lshrsi3_cnt1): Likewise. (ashrsi3_cnt1): Likewise. * config/arc/constraints.md (Rcq): Remove. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.cc | 48 +++++++---- gcc/config/arc/arc.md | 152 ++++++++++++++++------------------ gcc/config/arc/constraints.md | 20 ----- 3 files changed, 104 insertions(+), 116 deletions(-) diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index 7be27e01035..e6f52d87714 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -2474,6 +2474,20 @@ arc_setup_incoming_varargs (cumulative_args_t args_so_far, } } +/* Return TRUE if reg is ok for short instrcutions. */ + +static bool +arc_check_short_reg_p (rtx op) +{ + if (!REG_P (op)) + return false; + + if (IN_RANGE (REGNO (op) ^ 4, 4, 11)) + return true; + + return false; +} + /* Cost functions. */ /* Provide the costs of an addressing mode that contains ADDR. @@ -2485,7 +2499,7 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t, bool speed) switch (GET_CODE (addr)) { case REG : - return speed || satisfies_constraint_Rcq (addr) ? 0 : 1; + return speed || arc_check_short_reg_p (addr) ? 0 : 1; case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: case PRE_MODIFY: case POST_MODIFY: return !speed; @@ -2517,14 +2531,14 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t, bool speed) ? COSTS_N_INSNS (1) : speed ? 0 - : (satisfies_constraint_Rcq (plus0) + : (arc_check_short_reg_p (plus0) && satisfies_constraint_O (plus1)) ? 0 : 1); case REG: return (speed < 1 ? 0 - : (satisfies_constraint_Rcq (plus0) - && satisfies_constraint_Rcq (plus1)) + : (arc_check_short_reg_p (plus0) + && arc_check_short_reg_p (plus1)) ? 0 : 1); case CONST : case SYMBOL_REF : @@ -9003,8 +9017,8 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p) int intval = (REG_P (operands[2]) ? 1 : CONST_INT_P (operands[2]) ? INTVAL (operands[2]) : 0xbadc057); int neg_intval = -intval; - int short_0 = satisfies_constraint_Rcq (operands[0]); - int short_p = (!cond_p && short_0 && satisfies_constraint_Rcq (operands[1])); + int short_0 = arc_check_short_reg_p (operands[0]); + int short_p = (!cond_p && short_0 && arc_check_short_reg_p (operands[1])); int ret = 0; #define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \ @@ -9037,7 +9051,7 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p) patterns. */ if (short_p && ((REG_H_P (operands[2]) - && (match || satisfies_constraint_Rcq (operands[2]))) + && (match || arc_check_short_reg_p (operands[2]))) || (CONST_INT_P (operands[2]) && ((unsigned) intval <= (match ? 127 : 7))))) ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1"); @@ -9064,7 +9078,7 @@ arc_output_addsi (rtx *operands, bool cond_p, bool output_p) /* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */ if (TARGET_CODE_DENSITY && REG_P (operands[0]) && REG_P (operands[1]) && ((REGNO (operands[0]) == 0) || (REGNO (operands[0]) == 1)) - && satisfies_constraint_Rcq (operands[1]) + && arc_check_short_reg_p (operands[1]) && satisfies_constraint_L (operands[2])) ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;6"); } @@ -10033,7 +10047,7 @@ split_addsi (rtx *operands) /* Try for two short insns first. Lengths being equal, we prefer expansions with shorter register lifetimes. */ if (val > 127 && val <= 255 - && satisfies_constraint_Rcq (operands[0])) + && arc_check_short_reg_p (operands[0])) { operands[3] = operands[2]; operands[4] = gen_rtx_PLUS (SImode, operands[0], operands[1]); @@ -10057,8 +10071,8 @@ split_subsi (rtx *operands) /* Try for two short insns first. Lengths being equal, we prefer expansions with shorter register lifetimes. */ - if (satisfies_constraint_Rcq (operands[0]) - && satisfies_constraint_Rcq (operands[2])) + if (arc_check_short_reg_p (operands[0]) + && arc_check_short_reg_p (operands[2])) { if (val >= -31 && val <= 127) { @@ -10436,12 +10450,12 @@ arc_lra_p (void) return arc_lra_flag; } -/* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to use - Rcq registers, because some insn are shorter with them. OTOH we already - have separate alternatives for this purpose, and other insns don't - mind, so maybe we should rather prefer the other registers? - We need more data, and we can only get that if we allow people to - try all options. */ +/* ??? Should we define TARGET_REGISTER_PRIORITY? We might perfer to + use q registers, because some insn are shorter with them. OTOH we + already have separate alternatives for this purpose, and other + insns don't mind, so maybe we should rather prefer the other + registers? We need more data, and we can only get that if we allow + people to try all options. */ static int arc_register_priority (int r) { diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index e6fa2a1fbf6..458d3edf716 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -696,15 +696,13 @@ (define_expand "movqi" ; In order to allow the ccfsm machinery to do its work, the leading compact ; alternatives say 'canuse' - there is another alternative that will match ; when the condition codes are used. -; Rcq won't match if the condition is actually used; to avoid a spurious match -; via q, q is inactivated as constraint there. ; Likewise, the length of an alternative that might be shifted to conditional ; execution must reflect this, lest out-of-range branches are created. ; The iscompact attribute allows the epilogue expander to know for which ; insns it should lengthen the return insn. (define_insn "*movqi_insn" - [(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w, w,???w,h, w,Rcq, S,!*x, r,r, Ucm,m,???m, m,Usc") - (match_operand:QI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL, I,?Rac,i,?i, T,Rcq,Usd,Ucm,m,?Rac,c,?Rac,Cm3,i"))] + [(set (match_operand:QI 0 "move_dest_operand" "=q, q,r,q, h, w, w,???w,h, w,q,S,!*x, r,r, Ucm,m,???m, m,Usc") + (match_operand:QI 1 "move_src_operand" "rL,rP,q,P,hCm1,cL, I,?Rac,i,?i,T,q,Usd,Ucm,m,?Rac,c,?Rac,Cm3,i"))] "register_operand (operands[0], QImode) || register_operand (operands[1], QImode) || (satisfies_constraint_Cm3 (operands[1]) @@ -742,8 +740,8 @@ (define_expand "movhi" "if (prepare_move_operands (operands, HImode)) DONE;") (define_insn "*movhi_insn" - [(set (match_operand:HI 0 "move_dest_operand" "=Rcq,Rcq#q, w,Rcq#q, h, w, w,???w,Rcq#q,h, w,Rcq, S, r,r, Ucm,m,???m, m,VUsc") - (match_operand:HI 1 "move_src_operand" " cL, cP,Rcq#q, P,hCm1,cL, I,?Rac, i,i,?i, T,Rcq,Ucm,m,?Rac,c,?Rac,Cm3,i"))] + [(set (match_operand:HI 0 "move_dest_operand" "=q, q,r,q, h, w, w,???w,q,h, w,q,S, r,r, Ucm,m,???m, m,VUsc") + (match_operand:HI 1 "move_src_operand" " rL,rP,q,P,hCm1,cL, I,?Rac,i,i,?i,T,q,Ucm,m,?Rac,c,?Rac,Cm3,i"))] "register_operand (operands[0], HImode) || register_operand (operands[1], HImode) || (CONSTANT_P (operands[1]) @@ -793,8 +791,8 @@ (define_expand "movsi" ; the iscompact attribute allows the epilogue expander to know for which ; insns it should lengthen the return insn. (define_insn_and_split "*movsi_insn" ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 - [(set (match_operand:SI 0 "move_dest_operand" "=q, q,r,q, h, rl,r, r, r, r, ?r, r, q, h, rl, q, S, Us<,RcqRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m, m,VUsc") - (match_operand:SI 1 "move_src_operand" "rL,rP,q,P,hCm1,rLl,I,Clo,Chi,Cbi,Cpc,Clb,Cax,Cal,Cal,Uts,Rcq,RcqRck, Us>,Usd,Ucm, Usd, Ucd,m, r,!*Rzd,r,Cm3, C32"))] + [(set (match_operand:SI 0 "move_dest_operand" "=q, q,r,q, h, rl,r, r, r, r, ?r, r, q, h, rl, q, S, Us<,qRck,!*x, r,!*Rsd,!*Rcd,r,Ucm, Usd,m, m,VUsc") + (match_operand:SI 1 "move_src_operand" "rL,rP,q,P,hCm1,rLl,I,Clo,Chi,Cbi,Cpc,Clb,Cax,Cal,Cal,Uts,q,qRck, Us>,Usd,Ucm, Usd, Ucd,m, r,!*Rzd,r,Cm3, C32"))] "register_operand (operands[0], SImode) || register_operand (operands[1], SImode) || (CONSTANT_P (operands[1]) @@ -998,8 +996,8 @@ (define_insn_and_split "*tst_movb" (match_operand 0 "cc_register" "") (match_operator 4 "zn_compare_operator" [(and:SI - (match_operand:SI 1 "register_operand" "%Rcq,Rcq, c, c, c, c,Rrq,Rrq, c") - (match_operand:SI 2 "nonmemory_operand" "Rcq,C0p,cI,C1p,Ccp,Chs,Cbf,Cbf,???Cal")) + (match_operand:SI 1 "register_operand" "%q, q, c, c, c, c, q, q, c") + (match_operand:SI 2 "nonmemory_operand" "q,C0p,cI,C1p,Ccp,Chs,Cbf,Cbf,???Cal")) (const_int 0)])) (clobber (match_scratch:SI 3 "=X,X,X,X,X,X,Rrq,1,c"))] "TARGET_NPS_BITOPS" @@ -1014,9 +1012,9 @@ (define_insn "*tst" (match_operator 3 "zn_compare_operator" [(and:SI (match_operand:SI 1 "register_operand" - "%Rcq,Rcq, c, c, c, c, c, c") + "%q, q, c, c, c, c, c, c") (match_operand:SI 2 "nonmemory_operand" - " Rcq,C0p,cI,cL,C1p,Ccp,Chs,Cal")) + " q,C0p,cI,cL,C1p,Ccp,Chs,Cal")) (const_int 0)]))] "reload_completed || !satisfies_constraint_Cbf (operands[2]) @@ -1092,9 +1090,9 @@ (define_insn "*tst_bitfield" [(set (match_operand:CC_ZN 0 "cc_set_register" "") (match_operator 5 "zn_compare_operator" [(zero_extract:SI - (match_operand:SI 1 "register_operand" "%Rcqq,c, c,Rrq,c") - (match_operand:SI 2 "const_int_operand" "N,N, n,Cbn,n") - (match_operand:SI 3 "const_int_operand" "n,n,C_0,Cbn,n")) + (match_operand:SI 1 "register_operand" "%q,c, c,Rrq,c") + (match_operand:SI 2 "const_int_operand" "N,N, n,Cbn,n") + (match_operand:SI 3 "const_int_operand" "n,n,C_0,Cbn,n")) (const_int 0)])) (clobber (match_scratch:SI 4 "=X,X,X,Rrq,X"))] "" @@ -1678,7 +1676,7 @@ (define_insn "*movsicc_insn" "" { if (rtx_equal_p (operands[1], const0_rtx) && GET_CODE (operands[3]) == NE - && satisfies_constraint_Rcq (operands[0])) + && IN_RANGE (REGNO (operands[0]) ^ 4, 4, 11)) return "sub%?.ne %0,%0,%0"; /* ??? might be good for speed on ARC600 too, *if* properly scheduled. */ if ((optimize_size && (!TARGET_ARC600_FAMILY)) @@ -1980,8 +1978,8 @@ (define_expand "extendhisi2" ;; Absolute instructions (define_insn "abssi2" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,w,w") - (abs:SI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,Cal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,w,w") + (abs:SI (match_operand:SI 1 "nonmemory_operand" "q,cL,Cal")))] "" "abs%? %0,%1%&" [(set_attr "type" "two_cycle_core") @@ -2028,10 +2026,10 @@ (define_insn "sminsi3" ; We avoid letting this pattern use LP_COUNT as a register by specifying ; register class 'W' instead of 'w'. (define_insn_and_split "*addsi3_mixed" - ;; 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq, h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq, r,r, r, W, W,W, W,Rcqq, r, W") - (plus:SI (match_operand:SI 1 "register_operand" "%0, c, 0, Rcqq, 0, 0,Rcb, Rcqq, 0, 0,r, 0, c, c,0, 0, 0, 0, c") - (match_operand:SI 2 "nonmemory_operand" "cL, 0, Cm1, L,CL2,Csp,CM4,RcqqK, cO,rL,0,rCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))] + ;; 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, h,!*Rsd, q,Rcb, q, q, q, r,r, r, W, W,W, W, q, r, W") + (plus:SI (match_operand:SI 1 "register_operand" "%0,c, 0, q, 0, 0,Rcb, q, 0, 0,r, 0, c, c,0, 0, 0, 0, c") + (match_operand:SI 2 "nonmemory_operand" "cL,0, Cm1, L,CL2,Csp,CM4,qK,cO,rL,0,rCca,cLCmL,Cca,I,C2a,Cal,Cal,Cal")))] "" { arc_output_addsi (operands, arc_ccfsm_cond_exec_p (), true); @@ -2083,9 +2081,9 @@ (define_insn "mulhisi3_imm" ]) (define_insn "mulhisi3_reg" - [(set (match_operand:SI 0 "register_operand" "=Rcqq,r,r") - (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " 0,0,r")) - (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" "Rcqq,r,r"))))] + [(set (match_operand:SI 0 "register_operand" "=q,r,r") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0,r")) + (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" "q,r,r"))))] "TARGET_MPYW" "mpyw%? %0,%1,%2" [(set_attr "length" "*,4,4") @@ -2123,9 +2121,9 @@ (define_insn "umulhisi3_imm" ]) (define_insn "umulhisi3_reg" - [(set (match_operand:SI 0 "register_operand" "=Rcqq, r, r") - (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" " %0, 0, r")) - (zero_extend:SI (match_operand:HI 2 "register_operand" " Rcqq, r, r"))))] + [(set (match_operand:SI 0 "register_operand" "=q, r, r") + (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0, 0, r")) + (zero_extend:SI (match_operand:HI 2 "register_operand" "q, r, r"))))] "TARGET_MPYW" "mpyuw%? %0,%1,%2" [(set_attr "length" "*,4,4") @@ -2246,8 +2244,8 @@ (define_insn_and_split "mulsi64" (define_insn "mulsi_600" [(set (match_operand:SI 2 "mlo_operand" "") - (mult:SI (match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c") - (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,I,Cal"))) + (mult:SI (match_operand:SI 0 "register_operand" "%q,c,c,c") + (match_operand:SI 1 "nonmemory_operand" "q,cL,I,Cal"))) (clobber (match_operand:SI 3 "mhi_operand" ""))] "TARGET_MUL64_SET" "mul64%?\\t0,%0,%1" @@ -2282,8 +2280,8 @@ (define_insn_and_split "mulsidi_600" (define_insn "mul64" [(set (reg:DI MUL64_OUT_REG) (mult:DI - (sign_extend:DI (match_operand:SI 0 "register_operand" "%Rcq#q, c,c, c")) - (sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,L,C32"))))] + (sign_extend:DI (match_operand:SI 0 "register_operand" "%q, c,c, c")) + (sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "q,cL,L,C32"))))] "TARGET_MUL64_SET" "mul64%? \t0, %0, %1%&" [(set_attr "length" "*,4,4,8") @@ -2895,9 +2893,9 @@ (define_expand "subsi3" ; the casesi expander might generate a sub of zero, so we have to recognize it. ; combine should make such an insn go away. (define_insn_and_split "subsi3_insn" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,r, r,r,r,r, r, r, r") - (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,Rcqq,0,rL,r,L,I,Cal,Cal, r") - (match_operand:SI 2 "nonmemory_operand" "Rcqq,Rcqq,r, 0,r,r,0, 0, r,Cal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r, r,r,r,r, r, r, r") + (minus:SI (match_operand:SI 1 "nonmemory_operand" "0,q,0,rL,r,L,I,Cal,Cal, r") + (match_operand:SI 2 "nonmemory_operand" "q,q,r, 0,r,r,0, 0, r,Cal")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ @@ -3282,8 +3280,8 @@ (define_split ;;bic define_insn that allows limm to be the first operand (define_insn "*bicsi3_insn" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,r,r,r,r,r,r") - (and:SI (not:SI (match_operand:SI 1 "nonmemory_operand" "Rcqq,Lr,I,Cal,Lr,Cal,r")) + [(set (match_operand:SI 0 "dest_reg_operand" "=q,r,r,r,r,r,r") + (and:SI (not:SI (match_operand:SI 1 "nonmemory_operand" "q,Lr,I,Cal,Lr,Cal,r")) (match_operand:SI 2 "nonmemory_operand" "0,0,0,0,r,r,Cal")))] "" "@ @@ -3334,9 +3332,9 @@ (define_insn_and_split "iorsi3" (set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,nocond,canuse,nocond")]) (define_insn "xorsi3" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcq, r,r, r,r, r, r,r, r, r") - (xor:SI (match_operand:SI 1 "register_operand" "%0, Rcq, 0,r, 0,0, r, r,0, 0, r") - (match_operand:SI 2 "nonmemory_operand" " Rcqq, 0,rL,0,C0p,I,rL,C0p,I,Cal,Cal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, r,r, r,r, r, r,r, r, r") + (xor:SI (match_operand:SI 1 "register_operand" "%0,q, 0,r, 0,0, r, r,0, 0, r") + (match_operand:SI 2 "nonmemory_operand" "q,0,rL,0,C0p,I,rL,C0p,I,Cal,Cal")))] "" "* switch (which_alternative) @@ -3358,8 +3356,8 @@ (define_insn "xorsi3" (set_attr "cond" "canuse,canuse,canuse,canuse,canuse,canuse_limm,nocond,nocond,canuse_limm,canuse,nocond")]) (define_insn "negsi2" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,Rcqq,r,r") - (neg:SI (match_operand:SI 1 "register_operand" "0,Rcqq,0,r")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q,r,r") + (neg:SI (match_operand:SI 1 "register_operand" "0,q,0,r")))] "" "neg%?\\t%0,%1%&" [(set_attr "type" "unary") @@ -3367,8 +3365,8 @@ (define_insn "negsi2" (set_attr "predicable" "no,no,yes,no")]) (define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") - (not:SI (match_operand:SI 1 "register_operand" "Rcqq,c")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") + (not:SI (match_operand:SI 1 "register_operand" "q,c")))] "" "not%? %0,%1%&" [(set_attr "type" "unary,unary") @@ -3498,9 +3496,9 @@ (define_insn "*ashrsi3_insn" (set_attr "cond" "canuse,nocond,canuse,canuse,nocond,nocond")]) (define_insn "*lshrsi3_insn" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq,Rcqq,Rcqq, r, r, r") - (lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,Rcqq, 0, 0, r,rCal") - (match_operand:SI 2 "nonmemory_operand" "N, N,RcqqM,rL,rL,rCal")))] + [(set (match_operand:SI 0 "dest_reg_operand" "=q,q, q, r, r, r") + (lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "!0,q, 0, 0, r,rCal") + (match_operand:SI 2 "nonmemory_operand" "N,N,qM,rL,rL,rCal")))] "TARGET_BARREL_SHIFTER && (register_operand (operands[1], SImode) || register_operand (operands[2], SImode))" @@ -3546,8 +3544,8 @@ (define_expand "cbranchsi4" ;; modifed cc user if second, but not first operand is a compact register. (define_insn "cmpsi_cc_insn_mixed" [(set (reg:CC CC_REG) - (compare:CC (match_operand:SI 0 "register_operand" "Rcq#q,Rcqq, h, c, c,qRcq,c") - (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI,cL, Cal,Cal")))] + (compare:CC (match_operand:SI 0 "register_operand" "q, q, h, c, c, q,c") + (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,cL,Cal,Cal")))] "" "cmp%? %0,%B1%&" [(set_attr "type" "compare") @@ -3559,7 +3557,7 @@ (define_insn "cmpsi_cc_insn_mixed" (define_insn "*cmpsi_cc_zn_insn" [(set (reg:CC_ZN CC_REG) - (compare:CC_ZN (match_operand:SI 0 "register_operand" "qRcq,c") + (compare:CC_ZN (match_operand:SI 0 "register_operand" "q,c") (const_int 0)))] "" "tst%? %0,%0%&" @@ -3573,7 +3571,7 @@ (define_insn "*cmpsi_cc_zn_insn" (define_insn "*btst" [(set (reg:CC_ZN CC_REG) (compare:CC_ZN - (zero_extract:SI (match_operand:SI 0 "register_operand" "Rcqq,c") + (zero_extract:SI (match_operand:SI 0 "register_operand" "q,c") (const_int 1) (match_operand:SI 1 "nonmemory_operand" "L,Lc")) (const_int 0)))] @@ -3618,7 +3616,7 @@ (define_peephole2 (define_insn "*cmpsi_cc_z_insn" [(set (reg:CC_Z CC_REG) - (compare:CC_Z (match_operand:SI 0 "register_operand" "qRcq,c") + (compare:CC_Z (match_operand:SI 0 "register_operand" "q,c") (match_operand:SI 1 "p2_immediate_operand" "O,n")))] "" "@ @@ -3631,8 +3629,8 @@ (define_insn "*cmpsi_cc_z_insn" (define_insn "*cmpsi_cc_c_insn" [(set (reg:CC_C CC_REG) - (compare:CC_C (match_operand:SI 0 "register_operand" "Rcqq,Rcqq, h, c,Rcqq, c") - (match_operand:SI 1 "nonmemory_operand" "cO, hO,Cm1,cI, Cal,Cal")))] + (compare:CC_C (match_operand:SI 0 "register_operand" "q, q, h, c, q, c") + (match_operand:SI 1 "nonmemory_operand" "cO,hO,Cm1,cI,Cal,Cal")))] "" "cmp%? %0,%1%&" [(set_attr "type" "compare") @@ -3944,7 +3942,7 @@ (define_insn "jump_i" (const_int 2)))]) (define_insn "indirect_jump" - [(set (pc) (match_operand:SI 0 "nonmemory_operand" "L,I,Cal,Rcqq,r"))] + [(set (pc) (match_operand:SI 0 "nonmemory_operand" "L,I,Cal,q,r"))] "" "@ j%!%* %0%& @@ -4076,7 +4074,7 @@ (define_insn "casesi_load" ; Unlike the canonical tablejump, this pattern always uses a jump address, ; even for CASE_VECTOR_PC_RELATIVE. (define_insn "casesi_jump" - [(set (pc) (match_operand:SI 0 "register_operand" "Cal,Rcqq,c")) + [(set (pc) (match_operand:SI 0 "register_operand" "Cal,q,c")) (use (label_ref (match_operand 1 "" "")))] "" "j%!%* [%0]%&" @@ -4106,17 +4104,15 @@ (define_expand "call" } ") -; Rcq, which is used in alternative 0, checks for conditional execution. ; At instruction output time, if it doesn't match and we end up with ; alternative 1 ("q"), that means that we can't use the short form. (define_insn "*call_i" [(call (mem:SI (match_operand:SI 0 - "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) + "call_address_operand" "q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) (match_operand 1 "" "")) (clobber (reg:SI 31))] "" "@ - jl%!%* [%0]%& jl%!%* [%0]%& jl%!%* [%0] jli_s %S0 @@ -4126,10 +4122,10 @@ (define_insn "*call_i" jl%!%* %0 jl%* %0 jl%! %0" - [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") - (set_attr "iscompact" "maybe,false,*,true,*,*,*,*,*,*") - (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes") - (set_attr "length" "*,*,4,2,4,4,4,4,4,8")]) + [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") + (set_attr "iscompact" "maybe,*,true,*,*,*,*,*,*") + (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes") + (set_attr "length" "*,4,2,4,4,4,4,4,8")]) (define_expand "call_value" ;; operand 2 is stack_size_rtx @@ -4151,18 +4147,16 @@ (define_expand "call_value" XEXP (operands[1], 0) = force_reg (Pmode, callee); }") -; Rcq, which is used in alternative 0, checks for conditional execution. ; At instruction output time, if it doesn't match and we end up with ; alternative 1 ("q"), that means that we can't use the short form. (define_insn "*call_value_i" - [(set (match_operand 0 "dest_reg_operand" "=Rcq,q,w, w, w, w, w,w,w, w") + [(set (match_operand 0 "dest_reg_operand" "=q,w, w, w, w, w,w,w, w") (call (mem:SI (match_operand:SI 1 - "call_address_operand" "Rcq,q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) + "call_address_operand" "q,c,Cji,Csc,Cbp,Cbr,L,I,Cal")) (match_operand 2 "" ""))) (clobber (reg:SI 31))] "" "@ - jl%!%* [%1]%& jl%!%* [%1]%& jl%!%* [%1] jli_s %S1 @@ -4172,10 +4166,10 @@ (define_insn "*call_value_i" jl%!%* %1 jl%* %1 jl%! %1" - [(set_attr "type" "call,call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") - (set_attr "iscompact" "maybe,false,*,true,false,*,*,*,*,*") - (set_attr "predicable" "no,no,yes,no,no,yes,no,yes,no,yes") - (set_attr "length" "*,*,4,2,4,4,4,4,4,8")]) + [(set_attr "type" "call,call,call_no_delay_slot,call_no_delay_slot,call,call,call,call,call_no_delay_slot") + (set_attr "iscompact" "maybe,*,true,false,*,*,*,*,*") + (set_attr "predicable" "no,yes,no,no,yes,no,yes,no,yes") + (set_attr "length" "*,4,2,4,4,4,4,4,8")]) ; There is a bl_s instruction (16 bit opcode branch-and-link), but we can't ; use it for lack of inter-procedural branch shortening. @@ -4943,7 +4937,7 @@ (define_insn "*bbit" [(set (pc) (if_then_else (match_operator 3 "equality_comparison_operator" - [(zero_extract:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + [(zero_extract:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1) (match_operand:SI 2 "nonmemory_operand" "L,Lc")) (const_int 0)]) @@ -5153,7 +5147,7 @@ (define_insn "*cmpdf_" (set_attr "predicable" "yes")]) (define_insn "abssf2" - [(set (match_operand:SF 0 "dest_reg_operand" "=Rcq#q,r,r") + [(set (match_operand:SF 0 "dest_reg_operand" "=q,r,r") (abs:SF (match_operand:SF 1 "register_operand" "0,0,r")))] "" "bclr%?\\t%0,%1,31%&" @@ -5966,8 +5960,8 @@ (define_insn "*rotrsi3_cnt8" (set_attr "length" "4")]) (define_insn "*ashlsi2_cnt1" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") - (ashift:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") + (ashift:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" "asl%? %0,%1%&" @@ -5999,8 +5993,8 @@ (define_insn "*ashlsi2_cnt16" (set_attr "predicable" "no")]) (define_insn "*lshrsi3_cnt1" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" "lsr%? %0,%1%&" @@ -6009,8 +6003,8 @@ (define_insn "*lshrsi3_cnt1" (set_attr "predicable" "no,no")]) (define_insn "*ashrsi3_cnt1" - [(set (match_operand:SI 0 "dest_reg_operand" "=Rcqq,w") - (ashiftrt:SI (match_operand:SI 1 "register_operand" "Rcqq,c") + [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "q,c") (const_int 1)))] "" "asr%? %0,%1%&" diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md index 69ec4d53cac..38bda1230b8 100644 --- a/gcc/config/arc/constraints.md +++ b/gcc/config/arc/constraints.md @@ -432,26 +432,6 @@ (define_constraint "Csz" && !arc_legitimate_pic_addr_p (op) && !(satisfies_constraint_I (op) && optimize_size)")) -; Note that the 'cryptic' register constraints will not make reload use the -; associated class to reload into, but this will not penalize reloading of any -; other operands, or using an alternate part of the same alternative. - -; Rcq is different in three important ways from a register class constraint: -; - It does not imply a register class, hence reload will not use it to drive -; reloads. -; - It matches even when there is no register class to describe its accepted -; set; not having such a set again lessens the impact on register allocation. -; - It won't match when the instruction is conditionalized by the ccfsm. -(define_constraint "Rcq" - "@internal - Cryptic q - for short insn generation while not affecting register allocation - Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3}, - @code{r12}-@code{r15}" - (and (match_code "reg") - (match_test "TARGET_Rcq - && !arc_ccfsm_cond_exec_p () - && IN_RANGE (REGNO (op) ^ 4, 4, 11)"))) - (define_constraint "Rcb" "@internal Stack Pointer register @code{r28} - do not reload into its class" -- 2.30.2