From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id D7A663858439 for ; Mon, 10 Oct 2022 13:43:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D7A663858439 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1665409406tna159ck Received: from rios-cad5.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 10 Oct 2022 21:43:24 +0800 (CST) X-QQ-SSF: 01400000000000D0J000000A0000000 X-QQ-FEAT: mRz6/7wsmIgDHWh+nU373RurmiaRH+twE6ERHv/NB2j70da7lnVk9Yo36m+HK E/he10YcqE2PZtm62VzTBsH5nyA2Hk+RM95OqjcIymB/H3ICF3R8b7wNzl7jFl+zU7qw9+T 6283HrbwTuBYJH8j60t//LI4pdjQ68CYy7aCh9FbmJ7LiqUzKEmwCZPdZxRWEIaU75RB1rc Dvym3xQd9tV5WJfZAh7k0wlsLQl36bSog4ymQyu+7K7TFkqPacmDKfKXtk0+TqK7A7Wdsru ZMPvzFTCV7cthGrItcLs9I9kNdyyTATiKZ9VGcztYFrz5yGWoP3MjliEjsIPMhApJOnH7Rk exHNz2issag4Ppwk0ME7ypo4mEpOZ21rrBxmyHzYXKUiWkJajnqFvmZwZaEV5sA061j8om2 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add missing vsetvl instruction type. Date: Mon, 10 Oct 2022 21:43:22 +0800 Message-Id: <20221010134322.169275-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong When implementing built-in framework, I notice I missed vsetvl instruction type, so add it in a single patch preparing for the following patches. gcc/ChangeLog: * config/riscv/riscv.md: Add vsetvl instruction type. --- gcc/config/riscv/riscv.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 014206fb8bd..2d1cda2b98f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -229,6 +229,7 @@ ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read +;; vsetvl vector configuration-setting instrucions ;; 7. Vector Loads and Stores ;; vlde vector unit-stride load instructions ;; vste vector unit-stride store instructions @@ -316,7 +317,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts, + rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, -- 2.36.1