From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id CD2FF385803D; Fri, 14 Oct 2022 08:36:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CD2FF385803D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665736577; x=1697272577; h=from:to:cc:subject:date:message-id; bh=5PE1wd1vKLvP3Bv7eE5We6qkUtdl79xt2sPbQMHjLhg=; b=H4qI/PLGSXM+fKG5ZXgaHb9JfUXQcTjzmp+xEiSYnWbXyQi1S+fs29w8 IzlwSXHm463VQA25lZzOwFt303YuqXJx6TIUVC1EMhfaibGxMnhzWZ1VC 7x4bAYsTiGGX5QJ3SMv0+3YYe8zoTd9U5H/lx+ncgdVQu9cPP2WULgEqK 5lz4Gbp9is1SMRYEDKoEdhHXWMy52ShMMkFL+vVlzchdWnNSfF0t6cukj RkbLdXQwycnvt1DJFIA97iCZpXhSB2/SlbOiHHdwWGIKoe3/lywK4TrJf 6tfZmLMCnPzas7bGloe66FzqxT7I4ZcdBB0wspnl+PGjjZPOxbyU3P252 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="285046984" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="285046984" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 01:36:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="605300434" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="605300434" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 14 Oct 2022 01:36:09 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5BD471009C94; Fri, 14 Oct 2022 16:36:08 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: rguenther@suse.de, hongtao.liu@intel.com, ubizjak@gmail.com, richard.earnshaw@arm.com, richard.sandiford@arm.com, marcus.shawcroft@arm.com, kyrylo.tkachov@arm.com, rth@gcc.gnu.org, gnu@amylaar.uk, claziss@synopsys.com, nickc@redhat.com, ramana.radhakrishnan@arm.com, aoliva@gcc.gnu.org, hubicka@ucw.cz, mfortune@gmail.com, dje.gcc@gmail.com, segher@kernel.crashing.org, linkw@gcc.gnu.org, uweigand@de.ibm.com, krebbel@linux.ibm.com, olegendo@gcc.gnu.org, davem@redhat.com, ebotcazou@libertysurf.fr, jeffreyalaw@gmail.com, dave.anglin@bell.net Subject: [PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI Date: Fri, 14 Oct 2022 16:34:04 +0800 Message-Id: <20221014083406.8406-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, Sorry for the previous cover-letter stucking and disturbance and this is the right cover letter. These two patches aimed to add Intel PREFETCHI. The information is based on newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html The first patch added a fourth parameter for prefetch to align with LLVM in middle end. Currently LLVM had a fourth parameter to indicate what is prefetching. Also added a warning on backends that does not support instruction prefetch in machine description file to tell users attempting using prefetchi that the backend will change it to data prefetch. The second patch was i386 specific and added PREFETCHI to i386. Regtested on x86_64-pc-linux-gnu and cross-compiled to other backends. For other backends, I ran through the compile test and no regressions found. Since I did not have machines from other backends, could you kindly help me to test with other machines? I suppose there should not have regressions since I just added a warning to the md file and corresponding testcase. Ok for trunk? BRs, Haochen