From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id A8FB63AA9836 for ; Thu, 20 Oct 2022 09:33:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A8FB63AA9836 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAB3jnfCFVFjiiDzBQ--.8085S2; Thu, 20 Oct 2022 17:32:51 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn, jiawei Subject: [v4 PATCH 0/4] RISC-V: Support z*inx extensions. Date: Thu, 20 Oct 2022 17:32:31 +0800 Message-Id: <20221020093235.5071-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID:zQCowAB3jnfCFVFjiiDzBQ--.8085S2 X-Coremail-Antispam: 1UD129KBjvJXoW7tr13KFW8trW3Aw18ZrWDArb_yoW5Jr4DpF 4rGr4rAr98JFZa9r1xt3W8XFWYqwsag3yrCwn7Aw13C3yaqrW3JFyktw1fW3WUJa45Jr4f uFZ2kw45uw4jvrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkF14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE174l42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0pRCD7sUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiAwUFAGNQ7Y2bxAABsO X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Zfinx extension[1] had already ratified. Here is the implementation patch set that reuse floating point pattern and ban the use of fpr when use z*inx as a target. Current works can be find in follow links, binutils and simulator works already supported on upstream. https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase Thanks for Tariq Kurd, Kito Cheng, Jim Willson, Jeremy Bennett helped us a lot with this work. [1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf Version log: v2: As Kito Cheng's comment, add Changelog part in patches, update imply info in riscv-common.c, remove useless check and update annotation in riscv.c. v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as default, fix the lack of fcsr use in zfinx. v4: Rebase patch with upstream, add zhinx/zhinxmin extensions support. Add additional zhinx/zhinxmin same like zfh/zfhmin. Jiawei (4): RISC-V: Minimal support of z*inx extension. RISC-V: Target support for z*inx extension. RISC-V: Limit regs use for z*inx extension. RISC-V: Add zhinx/zhinxmin testcases. gcc/common/config/riscv/riscv-common.cc | 18 +++++ gcc/config/riscv/arch-canonicalize | 5 ++ gcc/config/riscv/constraints.md | 5 +- gcc/config/riscv/iterators.md | 6 +- gcc/config/riscv/riscv-builtins.cc | 4 +- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv-opts.h | 10 +++ gcc/config/riscv/riscv.cc | 21 ++++- gcc/config/riscv/riscv.md | 78 ++++++++++--------- gcc/config/riscv/riscv.opt | 3 + .../gcc.target/riscv/_Float16-zhinx-1.c | 10 +++ .../gcc.target/riscv/_Float16-zhinx-2.c | 9 +++ .../gcc.target/riscv/_Float16-zhinx-3.c | 9 +++ .../gcc.target/riscv/_Float16-zhinxmin-1.c | 10 +++ .../gcc.target/riscv/_Float16-zhinxmin-2.c | 10 +++ .../gcc.target/riscv/_Float16-zhinxmin-3.c | 10 +++ 16 files changed, 160 insertions(+), 50 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c -- 2.25.1