From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 73CE73AA980B for ; Thu, 20 Oct 2022 09:33:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 73CE73AA980B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowAB3jnfCFVFjiiDzBQ--.8085S3; Thu, 20 Oct 2022 17:32:51 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn, Jiawei Subject: [v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension. Date: Thu, 20 Oct 2022 17:32:32 +0800 Message-Id: <20221020093235.5071-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020093235.5071-1-jiawei@iscas.ac.cn> References: <20221020093235.5071-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID:zQCowAB3jnfCFVFjiiDzBQ--.8085S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAr1fKr1rAryrKFykJr43Wrg_yoWrtFWfpF Z5W3s0v34Fqa1fWa17try8W3yfX3WFgry5Jws7W34fAwsrJrZrAF90934S9r4kXFZ0vrn2 yw15C34Y9a1UWa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBF14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFjwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRZZ2hUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiAw8FAGNQ7Y2cFQAAsT X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Jiawei Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and 'zhinx/zhinxmin' corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension imply 'zicsr'. Co-Authored-By: Sinan Lin. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extensions. * config/riscv/arch-canonicalize: New imply relations. * config/riscv/riscv-opts.h (MASK_ZFINX): New mask. (MASK_ZDINX): Ditto. (MASK_ZHINX): Ditto. (MASK_ZHINXMIN): Ditto. (TARGET_ZFINX): New target. (TARGET_ZDINX): Ditto. (TARGET_ZHINX): Ditto. (TARGET_ZHINXMIN): Ditto. * config/riscv/riscv.opt: New target variable. --- gcc/common/config/riscv/riscv-common.cc | 18 ++++++++++++++++++ gcc/config/riscv/arch-canonicalize | 5 +++++ gcc/config/riscv/riscv-opts.h | 10 ++++++++++ gcc/config/riscv/riscv.opt | 3 +++ 4 files changed, 36 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index c39ed2e2696..55f3328df7a 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -51,6 +51,11 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, + {"zk", "zkn"}, {"zk", "zkr"}, {"zk", "zkt"}, @@ -99,6 +104,9 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, + + {"zhinx", "zhinxmin"}, + {"zhinxmin", "zfinx"}, {NULL, NULL} }; @@ -158,6 +166,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1168,6 +1181,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zinx_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zinx_subext, MASK_ZDINX}, + {"zhinx", &gcc_options::x_riscv_zinx_subext, MASK_ZHINX}, + {"zhinxmin", &gcc_options::x_riscv_zinx_subext, MASK_ZHINXMIN}, + {"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB}, {"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC}, {"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index fd7651ac491..2498db506b7 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -41,6 +41,11 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] IMPLIED_EXT = { "d" : ["f", "zicsr"], "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], + "zhinx" : ["zhinxmin", "zfinx", "zicsr"], + "zhinxmin" : ["zfinx", "zicsr"], + "zk" : ["zkn", "zkr", "zkt"], "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"], "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"], diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 55e0bc0a0e9..bb2322ad182 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,6 +83,16 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 1) +#define MASK_ZHINX (1 << 2) +#define MASK_ZHINXMIN (1 << 3) + +#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0) +#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0) +#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0) + #define MASK_ZBKB (1 << 0) #define MASK_ZBKC (1 << 1) #define MASK_ZBKX (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 8923a11a97d..7c1e0ed5f2d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -206,6 +206,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zinx_subext + TargetVariable int riscv_zk_subext -- 2.25.1