From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 014C0385840A for ; Mon, 24 Oct 2022 01:53:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 014C0385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp74t1666576426t9qrlrbd Received: from server1.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 24 Oct 2022 09:53:45 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: Fc2LLDWeHZ9VrZupq+PFQH5BcFI18/hyxNUnKS3IPp12lkFRsDSr0Or97hSGH Qn2yfA16c5iZDWPngP7CcFdydfJKS0GkkubyRW48qbKy4BKFFx/MegSFPwyODJkeSQW8/On JCCWRoOzGIpvOGhpDwVl0K2fdqqtDQE1leJtsvOKPAc9c+n/jafuQu0Sr0k0xdpyu8XHZqb 8z5jqUsjC9Y+7SDBxSV3w8PNAtmb9JOOb3pRTWOqvG1OY/RkdTlw90woaAqivkTG/XHwl9S qhj1/R47WVXDOM1EYf84v+10TWKY7lvID3zwQggY/sjhMUNywQsD6AbbI1aYC8Cj/PV+5ur U7YO5nVUlWSuDBuPZSXtqV3e1yF0fHQXdihcPU6bnxzpD3hhZrmPb6JRgasIDgIpPOVocVz X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Support (set (mem) (const_poly_int)) handling and remove TI/TF. Date: Mon, 24 Oct 2022 09:53:44 +0800 Message-Id: <20221024015344.22546-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-switch.def (ENTRY): Remove TI/TF. * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)). --- gcc/config/riscv/riscv-vector-switch.def | 4 ---- gcc/config/riscv/riscv.cc | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index cacfccb6d29..ee8ebd5f1cc 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64) ENTRY (VNx2DF, TARGET_VECTOR_FP64) ENTRY (VNx1DF, TARGET_VECTOR_FP64) -/* SEW = 128. Disable all of them. */ -ENTRY (VNx2TI, false) -ENTRY (VNx2TF, false) - #undef TARGET_VECTOR_FP32 #undef TARGET_VECTOR_FP64 #undef ENTRY diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 90a39047dd7..f7694ba043c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) { if (CONST_POLY_INT_P (src)) { + /* + Handle: + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156) + (const_int 96 [0x60])) [0 S1 A8]) + (const_poly_int:QI [8, 8])) + "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil)) + */ + if (MEM_P (dest)) + { + rtx tmp = gen_reg_rtx (mode); + emit_move_insn (tmp, src); + emit_move_insn (dest, tmp); + return true; + } poly_int64 value = rtx_to_poly_int64 (src); if (!value.is_constant () && !TARGET_VECTOR) { -- 2.36.1