From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id 1F19C385840A for ; Mon, 24 Oct 2022 02:03:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1F19C385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1666576994t21q40hq Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 24 Oct 2022 10:03:13 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: cn5tBnJDrK+iI4nr5eMuCr0JdS4hUmogmp7EEh/dYu2wbRU8jGQRZm3GHfZjA qzN+rETl7eKLM0wre3W8xVZ75f8SloOrqkDC47nIW1mgtQ1hGxKbCDPbKdz3jgOzEVcSAw+ Qp7qYEcYonO3DYWrKSbD3fzvUgypAruRqquEcHudUFtNxNaia5Be3Cy7STsEzBCDiPynhKM boBrPyjU6BromannUihj1dEgrUEhQm0H+RUDaItugHxvwTxp8pTbblnAk/GpJ/66WLk9AAQ ck/prUYgWUwjbQnJEGh8rhn559RrKRXVjpj2BNs8nB78pD1gggfZfHtux3gHfraH+tAaHLb w7aQ46kmnV/B9uxkce1aAqHaZuGxNi0d6Kak3KwZofK3+CEchY6mjcBZm2a28aJwtYBDUAu LlJqnTCBB5c= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Support (set (mem) (const_poly_int)) Date: Mon, 24 Oct 2022 10:03:12 +0800 Message-Id: <20221024020312.26851-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)). --- gcc/config/riscv/riscv.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 90a39047dd7..f7694ba043c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) { if (CONST_POLY_INT_P (src)) { + /* + Handle: + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156) + (const_int 96 [0x60])) [0 S1 A8]) + (const_poly_int:QI [8, 8])) + "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil)) + */ + if (MEM_P (dest)) + { + rtx tmp = gen_reg_rtx (mode); + emit_move_insn (tmp, src); + emit_move_insn (dest, tmp); + return true; + } poly_int64 value = rtx_to_poly_int64 (src); if (!value.is_constant () && !TARGET_VECTOR) { -- 2.36.1