From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 0824038582A8 for ; Mon, 24 Oct 2022 02:05:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0824038582A8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp82t1666577126tjlcqdzu Received: from server1.localdomain ( [42.247.22.65]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 24 Oct 2022 10:05:24 +0800 (CST) X-QQ-SSF: 01400000000000D0K000000A0000000 X-QQ-FEAT: ALw5QuVtm4WC7WQd6A6ihrVzLER2vbD1ERfujk7p4Yjh4dv206HS5/mdyji9N kZ5LJd+srNf8RlHApxwWJAeWyXkVYRRjUDjXWjjJ5TI2TGebYXnUHlGnNYXfCgnpRnQ7xVS UIwc0c2ttr2h+hEJCGKexsCNScjgK/pzLglS1+fK87q8mhjXAtRnU2Mdn3vfrqVs34sT5DH G3R4F7Za+PqxK3lHb2B6ep4Hl/Dy/p+cfPzLXgrpi6pZ91se3mxg75Nj5ahvfSf6k4fttHs jqFcDW5nzW0KTFsILmhNscjVAKMDbmda92yZAlUbxllZ3OT/fru8chQZ2d7FkqXPCVvkpj1 uf+FfG4E5D+mmkYMYlA5k99aV/f5tvqwUgvSl1EQtQ7k1t10W3oMA/255mVUg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Remove unused TI/TF vector modes. Date: Mon, 24 Oct 2022 10:05:24 +0800 Message-Id: <20221024020524.27704-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-switch.def (ENTRY): Remove unused TI/TF vector modes. --- gcc/config/riscv/riscv-vector-switch.def | 4 ---- 1 file changed, 4 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index cacfccb6d29..ee8ebd5f1cc 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -155,10 +155,6 @@ ENTRY (VNx4DF, TARGET_VECTOR_FP64) ENTRY (VNx2DF, TARGET_VECTOR_FP64) ENTRY (VNx1DF, TARGET_VECTOR_FP64) -/* SEW = 128. Disable all of them. */ -ENTRY (VNx2TI, false) -ENTRY (VNx2TF, false) - #undef TARGET_VECTOR_FP32 #undef TARGET_VECTOR_FP64 #undef ENTRY -- 2.36.1