From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id E1F8F3858C50 for ; Wed, 2 Nov 2022 12:52:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E1F8F3858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-05 (Coremail) with SMTP id zQCowACXrncgaGJjPM3jBw--.59559S3; Wed, 02 Nov 2022 20:52:49 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn, jiawei Subject: [RFC] RISC-V: Minimal supports for new extensions in profile. Date: Wed, 2 Nov 2022 20:52:34 +0800 Message-Id: <20221102125235.2325572-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221102125235.2325572-1-jiawei@iscas.ac.cn> References: <20221102125235.2325572-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:zQCowACXrncgaGJjPM3jBw--.59559S3 X-Coremail-Antispam: 1UD129KBjvJXoW3GFyfJF1rKr1ruw4xWF4Durg_yoW7XrW5pa 1kGa90vw1Fqw1aga1ftFWrJ345Za4fKrn3AF4UurW5Aa4DXrW8Ja4q9w13urykXF4rZry0 vw1UWw10934UCFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBF14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFjwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0pRZZ2hUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgQSAGNiWeYEMQACsV X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch just add name support contain in profiles. Set the extension version as 0.1. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extensions. * config/riscv/riscv-opts.h (MASK_ZICCAMOA): New mask. (MASK_ZICCIF): Ditto. (MASK_ZICCLSM): Ditto. (MASK_ZICCRSE): Ditto. (MASK_ZICNTR): Ditto. (MASK_ZIHINTPAUSE): Ditto. (MASK_ZIHPM): Ditto. (TARGET_ZICCAMOA): New target. (TARGET_ZICCIF): Ditto. (TARGET_ZICCLSM): Ditto. (TARGET_ZICCRSE): Ditto. (TARGET_ZICNTR): Ditto. (TARGET_ZIHINTPAUSE): Ditto. (TARGET_ZIHPM): Ditto. (MASK_SVPBMT): New mask. --- gcc/common/config/riscv/riscv-common.cc | 20 ++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 15 +++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index d6404a01205..602491c638d 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -163,6 +163,15 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"ziccamoa", ISA_SPEC_CLASS_NONE, 0, 1}, + {"ziccif", ISA_SPEC_CLASS_NONE, 0, 1}, + {"zicclsm", ISA_SPEC_CLASS_NONE, 0, 1}, + {"ziccrse", ISA_SPEC_CLASS_NONE, 0, 1}, + {"zicntr", ISA_SPEC_CLASS_NONE, 0, 1}, + + {"zihintpause", ISA_SPEC_CLASS_NONE, 0, 1}, + {"zihpm", ISA_SPEC_CLASS_NONE, 0, 1}, + {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -219,6 +228,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svpbmt", ISA_SPEC_CLASS_NONE, 0, 1}, /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} @@ -1179,6 +1189,14 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"ziccamoa", &gcc_options::x_riscv_zi_subext, MASK_ZICCAMOA}, + {"ziccif", &gcc_options::x_riscv_zi_subext, MASK_ZICCIF}, + {"zicclsm", &gcc_options::x_riscv_zi_subext, MASK_ZICCLSM}, + {"ziccrse", &gcc_options::x_riscv_zi_subext, MASK_ZICCRSE}, + {"zicntr", &gcc_options::x_riscv_zi_subext, MASK_ZICNTR}, + + {"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE}, + {"zihpm", &gcc_options::x_riscv_zi_subext, MASK_ZIHPM}, {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, @@ -1230,6 +1248,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zvl1024b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B}, {"zvl2048b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B}, {"zvl4096b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B}, + {"zvl8192b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B}, {"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B}, {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, @@ -1242,6 +1261,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"svpbmt", &gcc_options::x_riscv_sv_subext, MASK_SVPBMT}, {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 1dfe8c89209..906b6280188 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -69,9 +69,23 @@ enum stack_protector_guard { #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) +#define MASK_ZICCAMOA (1 << 2) +#define MASK_ZICCIF (1 << 3) +#define MASK_ZICCLSM (1 << 4) +#define MASK_ZICCRSE (1 << 5) +#define MASK_ZICNTR (1 << 6) +#define MASK_ZIHINTPAUSE (1 << 7) +#define MASK_ZIHPM (1 << 8) #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define TARGET_ZICCAMOA ((riscv_zi_subext & MASK_ZICCAMOA) != 0) +#define TARGET_ZICCIF ((riscv_zi_subext & MASK_ZICCIF) != 0) +#define TARGET_ZICCLSM ((riscv_zi_subext & MASK_ZICCLSM) != 0) +#define TARGET_ZICCRSE ((riscv_zi_subext & MASK_ZICCRSE) != 0) +#define TARGET_ZICNTR ((riscv_zi_subext & MASK_ZICNTR) != 0) +#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0) +#define TARGET_ZIHPM ((riscv_zi_subext & MASK_ZIHPM) != 0) #define MASK_ZBA (1 << 0) #define MASK_ZBB (1 << 1) @@ -174,6 +188,7 @@ enum stack_protector_guard { #define MASK_SVINVAL (1 << 0) #define MASK_SVNAPOT (1 << 1) +#define MASK_SVPBMT (1 << 2) #define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0) #define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0) -- 2.25.1