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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a13-20020a19f80d000000b00498f23c249dsm244877lff.74.2022.11.08.12.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 12:03:26 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Christoph Muellner , Vineet Gupta , Palmer Dabbelt , Jeff Law , Kito Cheng , Philipp Tomsich Subject: [PATCH] RISC-V: allow bseti on SImode without sign-extension Date: Tue, 8 Nov 2022 21:03:23 +0100 Message-Id: <20221108200323.2719563-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: As long as the SImode operand is not a partial subreg, we can use a bseti without postprocessing to or in a bit, as the middle end is smart enough to stay away from the signbit. gcc/ChangeLog: * config/riscv/bitmanip.md (*bsetidisi): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bexti-02.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/bitmanip.md | 12 +++++++++ gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index cbc00455b67..dddd3422c43 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -408,6 +408,18 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +;; As long as the SImode operand is not a partial subreg, we can use a +;; bseti without postprocessing, as the middle end is smart enough to +;; stay away from the signbit. +(define_insn "*bsetidisi" + [(set (match_operand:DI 0 "register_operand" "=r") + (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "single_bit_mask_operand" "i")))] + "TARGET_ZBS && TARGET_64BIT + && !partial_subreg_p (operands[2])" + "bseti\t%0,%1,%S2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bclr" [(set (match_operand:X 0 "register_operand" "=r") (and:X (rotate:X (const_int -2) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c new file mode 100644 index 00000000000..d3629946375 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +/* bexti */ +int f(int* a, int b) +{ + return ((*a << b) | (1 << 14)); +} + +int g(int a, int b) +{ + return ((a + b)| (1 << 30)); +} + +int h(int a, int b) +{ + return ((a + b)| (1ULL << 33)); +} + +/* { dg-final { scan-assembler-times "addw\t" 2 } } */ +/* { dg-final { scan-assembler-times "sllw\t" 1 } } */ +/* { dg-final { scan-assembler-times "bseti\t" 2 } } */ +/* { dg-final { scan-assembler-not "sext.w\t" } } */ + -- 2.34.1